參數(shù)資料
型號: MT48V4M32TG-8XT
元件分類: DRAM
英文描述: 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54
封裝: 0.400 INCH, PLASTIC, TSOP2-54
文件頁數(shù): 35/69頁
文件大?。?/td> 6213K
代理商: MT48V4M32TG-8XT
128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
40
2001 Micron Technology, Inc. All rights reserved.
NOTE:
1. This table applies when CKEn-1 was HIGH and CKEnis HIGH (see Table 9 on page 37) and after
tXSR has been met (if the
previous state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the com-
mands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given com-
mand is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no
register accesses are in progress.
Read:
A READ burst has been initiated, with auto precharge disabled, and has not yet terminated
or been terminated.
Write:
A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated
or been terminated.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when
tRP has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when
tRP has been met. Once tRP is met, the bank will be in the idle state.
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current
state only.
6. All states and sequences not shown are illegal or reserved.
Table 11:
Truth Table – CURRENT STATE BANK n, COMMAND TO BANK m
Notes: 1-6; notes appear below and on next page
CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION)
NOTES
Any
H
X
COMMAND INHIBIT (NOP/Continue previous operation)
LH
H
NO OPERATION (NOP/Continue previous operation)
Idle
X
Any Command Otherwise Allowed to Bank m
Row
Activating,
Active, or
Precharging
LL
H
ACTIVE (Select and activate row)
LH
L
H
READ (Select column and start READ burst)
7
LH
L
WRITE (Select column and start WRITE burst)
7
LL
H
L
PRECHARGE
Read
(Auto
Precharge
Disabled)
LL
H
ACTIVE (Select and activate row)
LH
L
H
READ (Select column and start new READ burst)
7, 10
LH
L
WRITE (Select column and start WRITE burst)
7, 11
LL
H
L
PRECHARGE
9
Write
(Auto
Precharge
Disabled)
LL
H
ACTIVE (Select and activate row)
LH
L
H
READ (Select column and start READ burst)
7, 12
LH
L
WRITE (Select column and start new WRITE burst)
7, 13
LL
H
L
PRECHARGE
9
Read
(With Auto
Precharge)
LL
H
ACTIVE (Select and activate row)
LH
L
H
READ (Select column and start new READ burst)
7, 8, 14
LH
L
WRITE (Select column and start WRITE burst)
7, 8, 15
LL
H
L
PRECHARGE
9
Write
(With Auto
Precharge)
LL
H
ACTIVE (Select and activate row)
LH
L
H
READ (Select column and start READ burst)
7, 8, 16
LH
L
WRITE (Select column and start new WRITE burst)
7, 8, 17
LL
H
L
PRECHARGE
9
相關(guān)PDF資料
PDF描述
MT48LC8M8A2TG-8EL:GIT 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54
MT4JSF6464HIY-80BXX 64M X 64 DDR DRAM MODULE, ZMA204
MT4JSF6464HY-1G4XX 64M X 64 DDR DRAM MODULE, ZMA204
MT4LC16M4A7DJ-6S 16M X 4 FAST PAGE DRAM, 60 ns, PDSO32
MT58L128L36P1T-5 128K X 36 CACHE SRAM, 2.8 ns, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述