參數(shù)資料
型號： MT48LC8M8A2TG-8EL:GIT
元件分類： DRAM
英文描述： 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝： 0.400 INCH, PLASTIC, TSOP2-54
文件頁數(shù)： 1/55頁
文件大?。?/td> 1454K
1
64Mb: x4, x8, x16 SDRAM
2002 Micron Technology, Inc.
64MSDRAM.pmd – Rev. H; Pub. 12/04
64Mb: x4, x8, x16
SDRAM
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
16 Meg x 4
8 Meg x 8
4 Meg x 16
Configuration
4 Meg x 4 x 4 banks
2 Meg x 8 x 4 banks
1 Meg x 16 x 4 banks
Refresh Count
4K
Row Addressing
4K (A0-A11)
Bank Addressing
4 (BA0, BA1)
Column Addressing
1K (A0-A9)
512 (A0-A8)
256 (A0-A7)
SYNCHRONOUS
DRAM
MT48LC16M4A2 – 4 Meg x 4
x 4 banks
MT48LC8M8A2 –
2 Meg x 8
x 4 banks
MT48LC4M16A2 – 1 Meg x 16 x 4 banks
For the latest data sheet, please refer to the Micron Web
PIN ASSIGNMENT (Top View)
54-Pin TSOP
FEATURES
PC66-, PC100-, and PC133-compliant
Fully synchronous; all signals registered on
positive edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
Self Refresh Modes: standard and low power
64ms, 4,096-cycle refresh
LVTTL-compatible inputs and outputs
Single +3.3V ±0.3V power supply
OPTIONS
MARKING
Configurations
16 Meg x 4
(4 Meg x 4
x 4 banks)
16M4
8 Meg x 8
(2 Meg x 8
x 4 banks)
8M8
4 Meg x 16 (1 Meg x 16 x 4 banks)
4M16
WRITE Recovery (tWR)
tWR = “2 CLK”1
A2
Plastic Package – OCPL2
54-pin TSOP II (400 mil)
TG
54-pin TSOP II (400 mil) Lead-free
P
Timing (Cycle Time)
10ns @ CL = 2 (PC100)
-8E 3,4,5
7.5ns @ CL = 3 (PC133)
-75
7.5ns @ CL = 2 (PC133)
-7E
6ns @ CL = 3 (PC133, x16 Only)
-6
Self Refresh
Standard
None
Low Power
L
Die Rev
:G
Operating Temperature Range
Commercial (0°C to +70°C)
None
Industrial (-40°C to +85°C)
IT 3
Part Number Example:
MT48LC8M8A2TG-75:G
NOTE: 1. Refer to Micron Technical Note: TN-48-05.
2. Off-center parting line.
3. Consult Micron for availability.
4. Not recommended for new designs.
5. Shown for PC100 compatibility.
VDD
DQ0
VDDQ
DQ1
DQ2
VssQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VssQ
DQ7
VDD
DQML
WE#
CAS#
RAS#
CS#
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
DQ15
VssQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VssQ
DQ10
DQ9
VDDQ
DQ8
Vss
NC
DQMH
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
x8
x16
x8
x4
-
DQ0
-
NC
DQ1
-
NC
DQ2
-
NC
DQ3
-
NC
-
NC
-
NC
-
NC
DQ0
-
NC
-
NC
DQ1
-
NC
-
NC
-
DQ7
-
NC
DQ6
-
NC
DQ5
-
NC
DQ4
-
NC
-
DQM
-
NC
-
NC
DQ3
-
NC
-
NC
DQ2
-
NC
-
DQM
-
Note:
The # symbol indicates signal is active LOW. A dash (–)
indicates x8 and x4 pin function is same as x16 pin function.
KEY TIMING PARAMETERS
SPEED
CLOCK
ACCESS TIME
SETUP
HOLD
GRADE
FREQUENCY
CL = 2* CL = 3*
TIME
-6
166 MHz
–
5.5ns
1.5ns
1ns
-7E
143 MHz
–
5.4ns
1.5ns
0.8ns
-75
133 MHz
–
5.4ns
1.5ns
0.8ns
-7E
133 MHz
5.4ns
–
1.5ns
0.8ns
-8E 3, 4, 5
125 MHz
–
6ns
2ns
1ns
-75
100 MHz
6ns
–
1.5ns
0.8ns
-8E 3, 4, 5
100 MHz
6ns
–
2ns
1ns
* CL = CAS (READ) latency
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