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參數(shù)資料
| 型號(hào)： | MT48LC4M32TG-10 |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁(yè)數(shù)： | 67/69頁(yè) |
| 文件大?。?/td> | 6213K |
| 代理商： | MT48LC4M32TG-10 |
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128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
7
2001 Micron Technology, Inc. All rights reserved.
mode is provided, along with a power-saving, power-
down mode. All inputs and outputs are LVTTL-com-
patible.
SDRAMs offer substantial advances in DRAM oper-
ating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks in order to hide precharge
time and the capability to randomly change column
addresses on each clock cycle during a burst access.
Figure 5: Functional Block Diagram 8 Meg x 16 SDRAM
12
RAS#
CAS#
ROW-
ADDRESS
MUX
CLK
CS#
WE#
CKE
CONTROL
LOGIC
COLUMN-
ADDRESS
COUNTER/
LATCH
MODE REGISTER
9
COMMAND
DECODE
A0-A11,
BA0, BA1
DQML,
DQMH
12
ADDRESS
REGISTER
14
512
(x16)
4096
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
COLUMN
DECODER
BANK0
MEMORY
ARRAY
(4,096 x 512 x 16)
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
4096
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
DQ0-
DQ15
16
DATA
INPUT
REGISTER
DATA
OUTPUT
REGISTER
16
12
BANK1
BANK2
BANK3
12
9
2
REFRESH
COUNTER
16
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