參數(shù)資料
型號(hào)： MT48LC4M32TG-10
元件分類： DRAM
英文描述： 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54
封裝： 0.400 INCH, PLASTIC, TSOP2-54
文件頁數(shù)： 32/69頁
文件大?。?/td> 6213K
代理商： MT48LC4M32TG-10
128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
38
2001 Micron Technology, Inc. All rights reserved.
NOTE:
1. This table applies when CKEn-1 was HIGH and CKEnis HIGH (see Table 9 on page 37) and after
tXSR has been met (if the
previous state was self refresh).
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are
those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
Arow in the bank has been activated, and tRCD has been met. No data bursts/accesses
and no register accesses are in progress.
Read:
A READ burst has been initiated, with auto precharge disabled, and has not yet termi-
nated or been terminated.
Write:
A WRITE burst has been initiated, with auto precharge disabled, and has not yet termi-
nated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP com-
mands, or allowable commands to the other bank should be issued on any clock edge occurring
during these states. Allowable commands to the other bank are determined by its current state
Precharging:
Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is
met, the bank will be in the idle state.
Row Activating:
Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is
met, the bank will be in the row active state.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when
tRP has been met. Once tRP is met, the bank will be in the idle state.
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must
be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH
command and ends when tRFC is met. Once tRFC is met, the SDRAM will be in the all banks idle state.
Accessing Mode
Register:
Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been
met. Once tMRD is met, the SDRAM will be in the all banks idle state.
Precharging All:
Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is
met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
Table 10:
Truth Table – Current State Bank n, Command To Bank n
Notes: 1-6; notes appear below table
CURRENT
STATE
CS#
RAS# CAS# WE# COMMAND (ACTION)
NOTES
Any
H
XXX
COMMAND INHIBIT (NOP/Continue previous operation)
L
HHH
NO OPERATION (NOP/Continue previous operation)
Idle
L
H
ACTIVE (Select and activate row)
LLL
H
AUTO REFRESH
LLLL
LOAD MODE REGISTER
LL
H
L
PRECHARGE
Row Active
LH
READ (Select column and start READ burst)
LH
L
WRITE (Select column and start WRITE burst)
LL
H
L
PRECHARGE (Deactivate row in bank or banks)
Read (Auto
Precharge
Disabled)
LH
READ (Select column and start new READ burst)
LH
L
WRITE (Select column and start WRITE burst)
LL
H
L
PRECHARGE (Truncate READ burst, start PRECHARGE)
LH
H
L
BURST TERMINATE
Write (Auto
Precharge
Disabled)
LH
READ (Select column and start READ burst)
LH
L
WRITE (Select column and start new WRITE burst)
LL
H
L
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
LH
H
L
BURST TERMINATE
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