- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄296642 > MT48LC4M32TG-10 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 PDF資料下載
參數(shù)資料
| 型號： | MT48LC4M32TG-10 |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 24/69頁 |
| 文件大?。?/td> | 6213K |
| 代理商： | MT48LC4M32TG-10 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁
128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
30
2001 Micron Technology, Inc. All rights reserved.
Fixed-length or full-page WRITE bursts can be trun-
cated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied coin-
cident with the BURST TERMINATE command will be
ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one
clock previous to the BURST TERMINATE command.
This is shown in Figure 26, where data n is the last
desired data element of a longer burst.
Figure 26: Terminating a WRITE Burst
Figure 27: PRECHARGE Command
PRECHARGE
The PRECHARGE command (see Figure 27) is used
to deactivate the open row in a particular bank or the
open row in all banks. The bank(s) will be available for
a subsequent row access some specified time (tRP)
after the precharge command is issued. Input A10
determines whether one or all banks are to be pre-
charged, and in the case where only one bank is to be
precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are
treated as “Don’t Care.” Once a bank has been pre-
charged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued
to that bank.
POWER-DOWN
Power-down occurs if CKE is registered low coinci-
dent with a NOP or COMMAND INHIBIT when no
accesses are in progress. If power-down occurs when
all banks are idle, this mode is referred to as precharge
power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as
active power-down. Entering power-down deactivates
the input and output buffers, excluding CKE, for maxi-
mum power savings while in standby. The device may
not remain in the power-down state longer than the
refresh period (64ms) since no refresh operations are
performed in this mode.
The power-down state is exited by registering a NOP
or COMMAND INHIBIT and CKE HIGH at the desired
CLK
DQ
T2
T1
T0
COMMAND
ADDRESS
BANK,
COL n
WRITE
BURST
TERMINATE
NEXT
COMMAND
DIN
n
(ADDRESS)
(DATA)
NOTE:
DQMs are LOW.
TRANSITIONING DATA
DON’T CARE
CS#
WE#
CAS#
RAS#
CKE
CLK
A10
DON’T CARE
HIGH
All Banks
Bank Selected
A0-A9
BA0,1
BANK
ADDRESS
VALID ADDRESS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT48V8M16LFB4-8XT | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| MT48LC4M32LFB5-10ES:G | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA90 |
| MT48V4M32TG-8XT | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| MT48LC8M8A2TG-8EL:GIT | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| MT4JSF6464HIY-80BXX | 64M X 64 DDR DRAM MODULE, ZMA204 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT48LC4M4A1 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM |
| MT48LC4M4A1TGS | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM |
| MT48LC4M4A2 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM |
| MT48LC64M4A2 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM |
| MT48LC64M4A2_03 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM 256Mb: x4, x8, x16 SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。