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參數(shù)資料
| 型號： | MT48LC4M32TG-10 |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 21/69頁 |
| 文件大?。?/td> | 6213K |
| 代理商： | MT48LC4M32TG-10 |
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128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
28
2001 Micron Technology, Inc. All rights reserved.
not be executed. An example is shown in Figure 24.
Data n + 1 is either the last of a burst of two or the last
desired of a longer burst.
Data for a fixed-length WRITE burst may be fol-
lowed by, or truncated with, a PRECHARGE command
to the same bank (provided that auto precharge was
not activated), and a full-page WRITE burst may be
truncated with a PRECHARGE command to the same
bank. The PRECHARGE command should be issued
tWR after the clock edge at which the last desired input
data element is registered. The auto precharge mode
requires a tWR of at least one clock plus time, regard-
less of frequency.
In addition, when truncating a WRITE burst, the
DQM signal must be used to mask input data for the
clock edge prior to, and the clock edge coincident with,
the PRECHARGE command. An example is shown in
Figure 25. Data n + 1 is either the last of a burst of two
or the last desired of a longer burst. Following the PRE-
CHARGE command, a subsequent command to the
same bank cannot be issued until tRP is met.
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the
command and address buses be available at the
appropriate time to issue the command; the advantage
of the PRECHARGE command is that it can be used to
truncate fixed-length or full-page bursts.
Figure 23: Random WRITE Cycles
Figure 24: WRITE to READ
DON’T CARE
CLK
DQ
DIN
n
T2
T1
T3
T0
COMMAND
ADDRESS
WRITE
BANK,
COL n
DIN
a
DIN
x
DIN
m
WRITE
BANK,
COL a
BANK,
COL x
BANK,
COL m
NOTES:
1) Each WRITE command may be to any bank.
2) DQM is LOW.
3) Example shows a burst of one, or an interrupting BL > 1.
TRANSITIONING DATA
DON’T CARE
CLK
DQ
T2
T1
T3
T0
COMMAND
ADDRESS
NOP
WRITE
BANK,
COL n
DIN
n
DIN
n + 1
DOUT
b
READ
NOP
BANK,
COL b
NOP
DOUT
b + 1
T4
T5
NOTES:
1) The WRITE command may be to any bank, and the READ command
may be to any bank.
2) DQM is LOW.
3) CAS latency = 2 for illustration.
4) Data n+1 is either the last data of a burst of two, or the last desired
of a longer burst.
TRANSITIONING DATA
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