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| 型號(hào)： | MT48LC4M32LFB5-10ES:G |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA90 |
| 封裝： | 8 X 13 MM, LEAD FREE, VFBGA-90 |
| 文件頁數(shù)： | 29/69頁 |
| 文件大?。?/td> | 6213K |
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128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
35
2001 Micron Technology, Inc. All rights reserved.
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto pre-
charge): A READ to bank m will interrupt a WRITE
on bank n when registered, with the data-out
appearing CAS latency later. The precharge to bank
n will begin after tWR is met, where tWR begins
when the READ to bank m is registered. The last
valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (Figure 33).
4. Interrupted by a WRITE (with or without auto pre-
charge): A WRITE to bank m will interrupt a WRITE
on bank n when registered. The precharge to bank n
will begin after tWR is met, where tWR begins when
the WRITE to bank m is registered. The last valid
data WRITE to bank n will be data registered one
clock prior to a WRITE to bank m (Figure 34).
Figure 33: WRITE With Auto Precharge Interrupted by a READ
DON’T CARE
CLK
DQ
T2
T1
T4
T3
T6
T5
T0
COMMAND
WRITE - AP
BANK n
NOP
DIN
a + 1
DIN
a
NOP
T7
BANK n
BANK m
ADDRESS
NOTE: 1. DQM is LOW.
BANK n,
COL a
BANK m,
COL d
READ - AP
BANK m
Internal
States
t
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
Page Active
READ with Burst of 4
t
tRP - BANK m
DOUT
d
DOUT
d + 1
CAS Latency = 3 (BANK m)
RP - BANK n
WR - BANK n
TRANSITIONING DATA
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