參數(shù)資料
型號(hào)： MT48LC4M32LFB5-10ES:G
元件分類： DRAM
英文描述： 4M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA90
封裝： 8 X 13 MM, LEAD FREE, VFBGA-90
文件頁(yè)數(shù)： 20/69頁(yè)
文件大小： 6213K
128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
27
2001 Micron Technology, Inc. All rights reserved.
WRITEs
WRITE bursts are initiated with a WRITE command,
as shown in Figure 20.
The starting column and bank addresses are pro-
vided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is pre-
charged at the completion of the burst. For the WRITE
commands used in the following illustrations, auto
precharge is disabled.
During WRITE bursts, the first valid data-in element
will be registered coincident with the WRITE com-
mand. Subsequent data elements will be registered on
each successive positive clock edge. Upon completion
of a fixed-length burst, assuming no other commands
have been initiated, the DQs will remain High-Z and
any additional input data will be ignored (see
Figure 21). A full-page burst will continue until termi-
nated. (At the end of the page, it will wrap to column 0
and continue.)
Figure 20: WRITE Command
Data for any WRITE burst may be truncated with a
subsequent WRITE command, and data for a fixed-
length WRITE burst may be immediately followed by
data for a WRITE command. The new WRITE com-
mand can be issued on any clock following the previ-
ous WRITE command, and the data provided
coincident with the new command applies to the new
command. An example is shown in Figure 21. Data n +
1 is either the last of a burst of two or the last desired of
a longer burst. The 128Mb SDRAM uses a pipelined
architecture and therefore does not require the 2n rule
associated with a prefetch architecture. A WRITE com-
mand can be initiated on any clock cycle following a
previous WRITE command. Full-speed random write
accesses within a page can be performed to the same
bank, as shown in Figure 22, or each subsequent
WRITE may be performed to a different bank.
Figure 21: WRITE Burst
Figure 22: WRITE to WRITE
Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixed-
length WRITE burst may be immediately followed by a
READ command. Once the READ command is regis-
tered, the data inputs will be ignored, and writes will
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
ADDRESS
DON’T CARE
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
ADDRESS
x16: A0-A8
x32: A0-A7
A10
BA0,1
A9, A11
VALID ADDRESS
CLK
DQ
DIN
n
T2
T1
T3
T0
COMMAND
ADDRESS
NOP
WRITE
DIN
n + 1
NOP
BANK,
COL n
NOTE:
Burst length = 2. DQM is LOW.
DON’T CARE
TRANSITIONING DATA
DON’T CARE
CLK
DQ
T2
T1
T0
COMMAND
ADDRESS
NOP
WRITE
BANK,
COL n
BANK,
COL b
DIN
n
DIN
n + 1
DIN
b
NOTE:
DQM is LOW. Each WRITE
command may be to any bank.
TRANSITIONING DATA
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