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| 型號： | MT48LC4M32LFB5-10ES:G |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA90 |
| 封裝： | 8 X 13 MM, LEAD FREE, VFBGA-90 |
| 文件頁數(shù)： | 15/69頁 |
| 文件大?。?/td> | 6213K |
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128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
22
2001 Micron Technology, Inc. All rights reserved.
This is shown in Figure 14 for CAS latencies of two and
three; data element n + 3 is either the last of a burst of
four or the last desired of a longer burst. The 128Mb
SDRAM uses a pipelined architecture and therefore
does not require the 2n rule associated with a prefetch
architecture. A READ command can be initiated on
any clock cycle following a previous READ command.
Full-speed random read accesses can be performed to
the same bank, as shown in Figure 15, or each subse-
quent READ may be performed to a different bank.
Figure 14: Consecutive READ Bursts
CLK
DQ
DOUT
n
T2
T1
T4
T3
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
NOP
BANK,
COL b
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
DOUT
b
READ
X = 0 cycles
NOTE: Each READ command may be to either bank. DQM is LOW. Shown with BL=4.
CAS Latency = 1
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
NOP
BANK,
COL b
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
DOUT
b
READ
X = 1 cycle
CAS Latency = 2
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
NOP
BANK,
COL b
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
DOUT
b
READ
NOP
T7
X = 2 cycles
CAS Latency = 3
DON’T CARE
TRANSITIONING DATA
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