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| 型號： | MT48LC4M32LFB5-10ES:G |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA90 |
| 封裝： | 8 X 13 MM, LEAD FREE, VFBGA-90 |
| 文件頁數(shù)： | 14/69頁 |
| 文件大?。?/td> | 6213K |
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128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
21
2001 Micron Technology, Inc. All rights reserved.
READs
READ bursts are initiated with a READ command, as
shown in Figure 12.
The starting column and bank addresses are pro-
vided with the READ command, and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is pre-
charged at the completion of the burst. For the READ
commands used in the following illustrations, auto
precharge is disabled.
During READ bursts, the valid data-out element
from the starting column address will be available fol-
lowing the CAS latency after the READ command.
Each subsequent data-out element will be valid by the
next positive clock edge. Figure 13 shows general tim-
ing for each possible CAS latency setting.
Figure 12: READ Command
Upon completion of a burst, assuming no other
commands have been initiated, the DQs will go High-
Z. A full-page burst will continue until terminated. (At
the end of the page, it will wrap to column 0 and con-
tinue.)
Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixed-
length READ burst may be immediately followed by
data from a READ command. In either case, a continu-
ous flow of data can be maintained. The first data ele-
ment from the new burst follows either the last
element of a completed burst or the last desired data
element of a longer burst that is being truncated. The
new READ command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one.
Figure 13: CAS Latency
DON’T CARE
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
ADDRESS
x16: A0-A8
x32: A0-A7
A10
BA0,1
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
ADDRESS
A9, A11
CLK
DQ
T2
T1
T3
T0
CAS Latency = 3
LZ
DOUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
T4
NOP
DON’T CARE
UNDEFINED
CLK
DQ
T2
T1
T0
CAS Latency = 1
LZ
DOUT
tOH
t
COMMAND
NOP
READ
tAC
CLK
DQ
T2
T1
T3
T0
CAS Latency = 2
LZ
DOUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
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