參數(shù)資料
型號: MT48H8M16LFB4-8IT:JTR
元件分類: DRAM
英文描述: 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54
封裝: 8 X 8 MM, LEAD FREE, VFBGA-54
文件頁數(shù): 4/61頁
文件大?。?/td> 2469K
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. A 6/06 EN
12
2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
Mode Register Definition
Preliminary
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ
command and the availability of the first piece of output data. The latency can be set to
one, two, or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQs will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a read command is registered at T0
and the latency is programmed to two clocks, the DQs will start driving after T1 and the
data will be valid by T2, as shown in Figure 5. Table 5 indicates the operating frequencies
at which each CAS latency setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
Figure 5:
CAS Latency
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use and/or test modes. The
programmed burst length applies to both read and write bursts.
Table 5:
CAS Latency
Speed
Allowable Operating Frequency (MHz)
CAS Latency = 2
CAS Latency = 3
-8
≤ 104
≤ 125
-10
≤ 83.3
≤ 104
CLK
DQ
T2
T1
T3
T0
CL = 3
LZ
DOUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
T4
NOP
DON’T CARE
UNDEFINED
CLK
DQ
T2
T1
T3
T0
CL = 2
LZ
DOUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
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