參數(shù)資料
型號(hào): MT48H8M16LFB4-8IT:JTR
元件分類: DRAM
英文描述: 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54
封裝: 8 X 8 MM, LEAD FREE, VFBGA-54
文件頁數(shù): 20/61頁
文件大?。?/td> 2469K
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. A 6/06 EN
27
2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
READs
Preliminary
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvan-
tage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length bursts.
Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command.
When truncating a WRITE burst, the input data applied coincident with the BURST
TERMINATE command will be ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one clock previous to the BURST
TERMINATE command. This is shown in Figure 23 on page 29, where data n is the last
desired data element of a longer burst.
Figure 19:
Random WRITE Cycles
Notes:
1. Each WRITE command may be to any bank. DQM is LOW.
Figure 20:
WRITE-To-READ
Notes:
1. The WRITE command may be to any bank, and the READ command may be to any bank.
DQM is LOW.
CLK
DQ
DIN
n
T2
T1
T0
COMMAND
ADDRESS
WRITE
BANK,
COL n
DIN
a
DIN
x
DIN
m
WRITE
BANK,
COL a
BANK,
COL x
BANK,
COL m
DON’T CARE
T3
CLK
DQ
COMMAND
ADDRESS
NOP
WRITE
BANK,
COL n
DIN
n
DIN
n + 1
DOUT
b
READ
NOP
BANK,
COL b
NOP
DOUT
b + 1
DON’T CARE
CL = 2
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相關(guān)代理商/技術(shù)參數(shù)
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