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| 型號(hào)： | MT47H64M16HR-3IT |
| 元件分類： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| 封裝： | 8 X 12.50 MM, ROHS COMPLIANT, FBGA-84 |
| 文件頁(yè)數(shù)： | 99/129頁(yè) |
| 文件大小： | 9252K |
| 代理商： | MT47H64M16HR-3IT |
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PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row activation
a specified time (tRP) after the PRECHARGE command is issued, except in the case of
concurrent auto precharge, where a READ or WRITE command to a different bank is
allowed as long as it does not interrupt the data transfer in the current bank and does
not violate any other timing parameters. After a bank has been precharged, it is in the
idle state and must be activated prior to any READ or WRITE commands being issued to
that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle
state) or if the previously open row is already in the process of precharging. However,
the precharge period will be determined by the last PRECHARGE command issued to
the bank.
REFRESH
REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to CAS#-
before-RAS# (CBR) REFRESH. All banks must be in the idle mode prior to issuing a
REFRESH command. This command is nonpersistent, so it must be issued each time a
refresh is required. The addressing is generated by the internal refresh controller. This
makes the address bits a “Don’t Care” during a REFRESH command.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if
the rest of the system is powered down. When in the self refresh mode, the DDR2
SDRAM retains data without external clocking. All power supply inputs (including Vref)
must be maintained at valid levels upon entry/exit and during SELF REFRESH operation.
The SELF REFRESH command is initiated like a REFRESH command except CKE is
LOW. The DLL is automatically disabled upon entering self refresh and is automatically
enabled upon exiting self refresh.
Mode Register (MR)
The mode register is used to define the specific mode of operation of the DDR2 SDRAM.
This definition includes the selection of a burst length, burst type, CAS latency, operat-
ing mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 35
(page 72). Contents of the mode register can be altered by re-executing the LOAD
MODE (LM) command. If the user chooses to modify only a subset of the MR variables,
all variables must be programmed when the command is issued.
The MR is programmed via the LM command and will retain the stored information
until it is programmed again or until the device loses power (except for bit M8, which is
self-clearing). Reprogramming the mode register will not alter the contents of the mem-
ory array, provided it is performed correctly.
The LM command can only be issued (or reissued) when all banks are in the precharged
state (idle state) and no bursts are in progress. The controller must wait the specified
time tMRD before initiating any subsequent operations such as an ACTIVATE com-
mand. Violating either of these requirements will result in an unspecified operation.
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
Mode Register (MR)
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
71
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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| MT48V8M16LFB4-8XT | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H64M16HR-3L | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
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