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參數(shù)資料
| 型號： | MT47H64M16HR-3IT |
| 元件分類： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| 封裝： | 8 X 12.50 MM, ROHS COMPLIANT, FBGA-84 |
| 文件頁數(shù)： | 86/129頁 |
| 文件大?。?/td> | 9252K |
| 代理商： | MT47H64M16HR-3IT |
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List of Figures
Figure 1: 1Gb DDR2 Part Numbers ................................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................... 8
Figure 3: 256 Meg x 4 Functional Block Diagram ............................................................................................. 11
Figure 4: 128 Meg x 8 Functional Block Diagram ............................................................................................. 12
Figure 5: 64 Meg x 16 Functional Block Diagram ............................................................................................. 13
Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 14
Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View) .............................................................................. 15
Figure 8: 84-Ball FBGA Package (8mm x 12.5mm) – x16 ................................................................................... 18
Figure 9: 60-Ball FBGA Package (8mm x 11.5mm) – x4, x8 ............................................................................... 19
Figure 10: 60-Ball FBGA (8mm x 10mm) – x4, x8 ............................................................................................. 20
Figure 11: Example Temperature Test Point Location ..................................................................................... 23
Figure 12: Single-Ended Input Signal Levels ................................................................................................... 40
Figure 13: Differential Input Signal Levels ...................................................................................................... 41
Figure 14: Differential Output Signal Levels .................................................................................................... 43
Figure 15: Output Slew Rate Load .................................................................................................................. 44
Figure 16: Full Strength Pull-Down Characteristics ......................................................................................... 45
Figure 17: Full Strength Pull-Up Characteristics ............................................................................................. 46
Figure 18: Reduced Strength Pull-Down Characteristics ................................................................................. 47
Figure 19: Reduced Strength Pull-Up Characteristics ...................................................................................... 48
Figure 20: Input Clamp Characteristics .......................................................................................................... 49
Figure 21: Overshoot ..................................................................................................................................... 50
Figure 22: Undershoot .................................................................................................................................. 50
Figure 23: Nominal Slew Rate for tIS .............................................................................................................. 55
Figure 24: Tangent Line for tIS ....................................................................................................................... 55
Figure 25: Nominal Slew Rate for tIH .............................................................................................................. 56
Figure 26: Tangent Line for tIH ...................................................................................................................... 56
Figure 27: Nominal Slew Rate for tDS ............................................................................................................. 61
Figure 28: Tangent Line for tDS ...................................................................................................................... 61
Figure 29: Nominal Slew Rate for tDH ............................................................................................................ 62
Figure 30: Tangent Line for tDH ..................................................................................................................... 62
Figure 31: AC Input Test Signal Waveform Command/Address Balls ............................................................... 63
Figure 32: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ........................................... 63
Figure 33: AC Input Test Signal Waveform for Data with DQS (Single-Ended) .................................................. 64
Figure 34: AC Input Test Signal Waveform (Differential) ................................................................................. 64
Figure 35: MR Definition ............................................................................................................................... 72
Figure 36: CL ................................................................................................................................................ 75
Figure 37: EMR Definition ............................................................................................................................. 76
Figure 38: READ Latency ............................................................................................................................... 79
Figure 39: WRITE Latency ............................................................................................................................. 79
Figure 40: EMR2 Definition ........................................................................................................................... 80
Figure 41: EMR3 Definition ........................................................................................................................... 81
Figure 42: DDR2 Power-Up and Initialization ................................................................................................. 83
Figure 43: Example: Meeting tRRD (MIN) and tRCD (MIN) .............................................................................. 86
Figure 44: Multibank Activate Restriction ....................................................................................................... 87
Figure 45: READ Latency ............................................................................................................................... 89
Figure 46: Consecutive READ Bursts .............................................................................................................. 90
Figure 47: Nonconsecutive READ Bursts ........................................................................................................ 91
Figure 48: READ Interrupted by READ ........................................................................................................... 92
Figure 49: READ-to-WRITE ............................................................................................................................ 92
Figure 50: READ-to-PRECHARGE – BL = 4 ...................................................................................................... 93
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
6
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H64M16HR-3L | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
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