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| 型號： | MT47H64M16HR-3IT |
| 元件分類： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| 封裝： | 8 X 12.50 MM, ROHS COMPLIANT, FBGA-84 |
| 文件頁數(shù)： | 50/129頁 |
| 文件大?。?/td> | 9252K |
| 代理商： | MT47H64M16HR-3IT |
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Table 10: DDR2 IDD Specifications and Conditions (Die Revision G) (Continued)
Notes: 1–7 apply to the entire table
Parameter/Condition
Symbol
Configuration
VDD
-25E/-25
-3E/-3
-37E
Units
Operating burst write current: All
banks open, continuous burst writes; BL
= 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are
switching; Data bus inputs are switching
IDD4W
x4
1.9
145
120
110
mA
1.6
120
95
85
x8
1.9
160
135
125
1.6
130
110
95
x16
1.9
315
200
180
1.6
255
165
140
Operating burst read current: All
banks open, continuous burst reads,
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
tRP = tRP (IDD); CKE is HIGH, CS# is HIGH
between valid commands; Address bus
inputs are switching; Data bus inputs
are switching
IDD4R
x4
1.9
145
120
110
mA
1.6
120
95
80
x8
1.9
160
135
125
1.6
130
110
90
x16
1.9
320
220
180
1.6
260
180
140
Burst refresh current: tCK = tCK (IDD);
REFRESH command at every tRFC (IDD) in-
terval; CKE is HIGH, CS# is HIGH be-
tween valid commands; Other control
and address bus inputs are switching; Da-
ta bus inputs are switching
IDD5
x4, x8
1.9
235
215
210
mA
1.6
190
180
175
x16
1.9
280
270
250
1.6
225
220
210
Self refresh current: CK and CK# at
0V; CKE
≤ 0.2V; Other control and ad-
dress bus inputs are floating; Data bus
inputs are floating
IDD6
x4, x8, x16
1.9
7
mA
1.6
7
Operating bank interleave read
current: All bank interleaving reads,
IOUT = 0mA; BL = 4, CL = CL (IDD),
AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK
(IDD), tRC = tRC (IDD), tRRD = tRRD (IDD),
tRCD = tRCD (IDD); CKE is HIGH, CS# is
HIGH between valid commands; Address
bus inputs are stable during deselects;
Data bus inputs are switching; See IDD7
Conditions (page 25) for details
IDD7
x4, x8
1.9
335
280
270
mA
1.6
250
225
220
x16
1.9
440
350
330
1.6
330
280
270
Notes: 1. IDD specifications are tested after the device is properly initialized. 0°C ≤ TC ≤ +85°C.
2. VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VDDL = +1.8V ±0.1V, VREF = VDDQ/2.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and
UDQS#. IDD values must be met with all combinations of EMR bits 10 and 11.
5. Definitions for IDD conditions:
LOW
VIN ≤ VIL(AC)max
HIGH
VIN ≥ VIH(AC)min
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
Electrical Specifications – IDD Parameters
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
27
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H64M16HR-3L | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
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