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| 型號(hào)： | MT47H64M16HR-3IT |
| 元件分類： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| 封裝： | 8 X 12.50 MM, ROHS COMPLIANT, FBGA-84 |
| 文件頁(yè)數(shù)： | 115/129頁(yè) |
| 文件大小： | 9252K |
| 代理商： | MT47H64M16HR-3IT |
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ACTIVATE
Before any READ or WRITE commands can be issued to a bank within the DDR2
SDRAM, a row in that bank must be opened (activated), even when additive latency is
used. This is accomplished via the ACTIVATE command, which selects both the bank
and the row to be activated.
After a row is opened with an ACTIVATE command, a READ or WRITE command may
be issued to that row subject to the tRCD specification. tRCD (MIN) should be divided
by the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVATE command on which a READ or WRITE command can be
entered. The same procedure is used to convert other specification limits from time
units to clock cycles. For example, a tRCD (MIN) specification of 20ns with a 266 MHz
which covers any case where 5 < tRCD (MIN)/tCK
≤ 6. Figure 43 also shows the case for
tRRD where 2 < tRRD (MIN)/tCK
≤ 3.
Figure 43: Example: Meeting tRRD (MIN) and tRCD (MIN)
Command
Don’t Care
T1
T0
T2
T3
T4
T5
T6
T7
tRRD
Row
Col
Bank x
Bank y
Row
Bank z
Bank y
NOP
ACT
NOP
ACT
NOP
RD/WR
tRCD
CK#
Address
Bank address
CK
T8
T9
NOP
A subsequent ACTIVATE command to a different row in the same bank can only be is-
sued after the previous active row has been closed (precharged). The minimum time
interval between successive ACTIVATE commands to the same bank is defined by tRC.
A subsequent ACTIVATE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The mini-
mum time interval between successive ACTIVATE commands to different banks is
defined by tRRD.
DDR2 devices with 8 banks (1Gb or larger) have an additional requirement: tFAW. This
requires no more than four ACTIVATE commands may be issued in any given tFAW
(MIN) period, as shown in Figure 44 (page 87).
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
ACTIVATE
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
86
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H64M16HR-3L | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
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