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參數(shù)資料
| 型號： | MT47H64M16HR-3IT |
| 元件分類： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| 封裝： | 8 X 12.50 MM, ROHS COMPLIANT, FBGA-84 |
| 文件頁數(shù)： | 106/129頁 |
| 文件大?。?/td> | 9252K |
| 代理商： | MT47H64M16HR-3IT |
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On-Die Termination (ODT)
ODT effective resistance, RTT(EFF), is defined by bits E2 and E6 of the EMR, as shown in
Figure 37 (page 76). The ODT feature is designed to improve signal integrity of the mem-
ory channel by allowing the DDR2 SDRAM controller to independently turn on/off ODT
for any or all devices. RTT effective resistance values of 50Ω, 75Ω, and 150Ω are selecta-
ble and apply to each DQ, DQS/DQS#, RDQS/RDQS#, UDQS/UDQS#, LDQS/LDQS#,
DM, and UDM/LDM signals. Bits (E6, E2) determine what ODT resistance is enabled by
turning on/off “sw1,” “sw2,” or “sw3.” The ODT effective resistance value is selected by
enabling switch “sw1,” which enables all R1 values that are
150Ω each, enabling an ef-
fective resistance of
75Ω (RTT2 [EFF] = R2/2). Similarly, if “sw2” is enabled, all R2 values
that are
300Ω each, enable an effective ODT resistance of 150Ω (RTT2[EFF] = R2/2).
Switch “sw3” enables R1 values of
100Ω, enabling effective resistance of 50Ω. Reserved
states should not be used, as an unknown operation or incompatibility with future ver-
sions may result.
The ODT control ball is used to determine when RTT(EFF) is turned on and off, assuming
ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and ODT input
ball are only used during active, active power-down (both fast-exit and slow-exit
modes), and precharge power-down modes of operation.
ODT must be turned off prior to entering self refresh mode. During power-up and initi-
alization of the DDR2 SDRAM, ODT should be disabled until the EMR command is
issued. This will enable the ODT feature, at which point the ODT ball will determine the
RTT(EFF) value. Anytime the EMR enables the ODT function, ODT may not be driven
HIGH until eight clocks after the EMR has been enabled (see Figure 80 (page 124) for
ODT timing diagrams).
Off-Chip Driver (OCD) Impedance Calibration
The OFF-CHIP DRIVER function is an optional DDR2 JEDEC feature not supported by
Micron and thereby must be set to the default state. Enabling OCD beyond the default
settings will alter the I/O drive characteristics and the timing and output I/O specifica-
tions will no longer be valid (see Initialization (page 82) for proper setting of OCD
defaults).
Posted CAS Additive Latency (AL)
Posted CAS additive latency (AL) is supported to make the command and data bus effi-
cient for sustainable bandwidths in DDR2 SDRAM. Bits E3–E5 define the value of AL, as
shown in Figure 37. Bits E3–E5 allow the user to program the DDR2 SDRAM with an AL
of 0, 1, 2, 3, 4, 5, or 6 clocks. Reserved states should not be used as an unknown opera-
tion or incompatibility with future versions may result.
In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued
prior to tRCD (MIN) with the requirement that AL
≤ tRCD (MIN). A typical application
using this feature would set AL = tRCD (MIN) - 1 × tCK. The READ or WRITE command
is held for the time of the AL before it is issued internally to the DDR2 SDRAM device.
RL is controlled by the sum of AL and CL; RL = AL + CL. WRITE latency (WL) is equal to
(page 79). An example of a WL is shown in Figure 39 (page 79).
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
Extended Mode Register (EMR)
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
78
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H64M16HR-3L | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
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