參數(shù)資料
型號： MT47H128M8HQ-3AT
元件分類： DRAM
英文描述： 128M X 8 DDR DRAM, 0.4 ns, PBGA60
封裝： 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60
文件頁數(shù)： 97/129頁
文件大?。?/td> 9252K
代理商： MT47H128M8HQ-3AT
Figure 51: READ-to-PRECHARGE – BL = 8 ...................................................................................................... 93
Figure 52: Bank Read – Without Auto Precharge ............................................................................................. 95
Figure 53: Bank Read – with Auto Precharge ................................................................................................... 96
Figure 55: x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window ...................................................... 98
Figure 56: Data Output Timing – tAC and tDQSCK .......................................................................................... 99
Figure 57: Write Burst ................................................................................................................................... 101
Figure 58: Consecutive WRITE-to-WRITE ...................................................................................................... 102
Figure 59: Nonconsecutive WRITE-to-WRITE ................................................................................................ 102
Figure 60: WRITE Interrupted by WRITE ....................................................................................................... 103
Figure 61: WRITE-to-READ ........................................................................................................................... 104
Figure 62: WRITE-to-PRECHARGE ................................................................................................................ 105
Figure 63: Bank Write – Without Auto Precharge ............................................................................................ 106
Figure 64: Bank Write – with Auto Precharge ................................................................................................. 107
Figure 65: WRITE – DM Operation ................................................................................................................ 108
Figure 66: Data Input Timing ........................................................................................................................ 109
Figure 67: Refresh Mode ............................................................................................................................... 110
Figure 68: Self Refresh .................................................................................................................................. 112
Figure 69: Power-Down ................................................................................................................................ 114
Figure 70: READ-to-Power-Down or Self Refresh Entry .................................................................................. 116
Figure 71: READ with Auto Precharge-to-Power-Down or Self Refresh Entry .................................................. 116
Figure 72: WRITE-to-Power-Down or Self Refresh Entry ................................................................................ 117
Figure 74: REFRESH Command-to-Power-Down Entry ................................................................................. 118
Figure 75: ACTIVATE Command-to-Power-Down Entry ................................................................................ 118
Figure 76: PRECHARGE Command-to-Power-Down Entry ............................................................................ 119
Figure 77: LOAD MODE Command-to-Power-Down Entry ............................................................................ 119
Figure 79: RESET Function ........................................................................................................................... 122
Figure 80: ODT Timing for Entering and Exiting Power-Down Mode .............................................................. 124
Figure 81: Timing for MRS Command to ODT Update Delay .......................................................................... 125
Figure 82: ODT Timing for Active or Fast-Exit Power-Down Mode ................................................................. 125
Figure 83: ODT Timing for Slow-Exit or Precharge Power-Down Modes ......................................................... 126
Figure 84: ODT Turn-Off Timings When Entering Power-Down Mode ............................................................ 126
Figure 85: ODT Turn-On Timing When Entering Power-Down Mode ............................................................. 127
Figure 86: ODT Turn-Off Timing When Exiting Power-Down Mode ............................................................... 128
Figure 87: ODT Turn-On Timing When Exiting Power-Down Mode ................................................................ 129
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT47H128M8HQ-3EAT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
MT47H128M8HQ-3EIT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
MT47H128M8HQ-3EL 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
MT47H128M8HQ-3IT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
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