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| 型號： | MT47H128M8HQ-3AT |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| 封裝： | 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60 |
| 文件頁數(shù)： | 95/129頁 |
| 文件大?。?/td> | 9252K |
| 代理商： | MT47H128M8HQ-3AT |
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Table 38: Truth Table – Current State Bank n – Command to Bank m
Notes: 1–6 apply to the entire table
Current State
CS#
RAS#
CAS#
WE#
Command/Action
Notes
Any
H
X
DESELECT (NOP/continue previous operation)
L
H
NO OPERATION (NOP/continue previous operation)
Idle
X
Any command otherwise allowed to bank m
Row
active, active,
or precharge
L
H
ACTIVATE (select and activate row)
L
H
L
H
READ (select column and start READ burst)
L
H
L
WRITE (select column and start WRITE burst)
L
H
L
PRECHARGE
Read (auto
precharge
disabled)
L
H
ACTIVATE (select and activate row)
L
H
L
H
READ (select column and start new READ burst)
L
H
L
WRITE (select column and start WRITE burst)
L
H
L
PRECHARGE
Write (auto pre-
charge
disabled)
L
H
ACTIVATE (select and activate row)
L
H
L
H
READ (select column and start READ burst)
L
H
L
WRITE (select column and start new WRITE burst)
L
H
L
PRECHARGE
Read (with
auto
precharge)
L
H
ACTIVATE (select and activate row)
L
H
L
H
READ (select column and start new READ burst)
L
H
L
WRITE (select column and start WRITE burst)
L
H
L
PRECHARGE
Write (with
auto
precharge)
L
H
ACTIVATE (select and activate row)
L
H
L
H
READ (select column and start READ burst)
L
H
L
WRITE (select column and start new WRITE burst)
L
H
L
PRECHARGE
Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSNR has been
met (if the previous state was self refresh).
2. This table describes an alternate bank operation, except where noted (the current state
is for bank n and the commands shown are those allowed to be issued to bank m, assum-
ing that bank m is in such a state that the given command is allowable). Exceptions are
covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, tRP has been met, and any READ
burst is complete.
Row active:
A row in the bank has been activated and tRCD has been met.
No data bursts/accesses and no register accesses are in progress.
Read:
A READ burst has been initiated with auto precharge disabled
and has not yet terminated.
Write:
A WRITE burst has been initiated with auto precharge disabled
and has not yet terminated.
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
Commands
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
68
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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PDF描述 |
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| MT47H64M16HR-3IT | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| MT48H8M16LFB4-8IT:JTR | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| MT48LC4M32TG-10 | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H128M8HQ-3EAT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HQ-3EIT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HQ-3EL | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HQ-3IT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
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