參數(shù)資料
型號： MT47H128M8HQ-3AT
元件分類： DRAM
英文描述： 128M X 8 DDR DRAM, 0.4 ns, PBGA60
封裝： 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60
文件頁數(shù)： 52/129頁
文件大?。?/td> 9252K
代理商： MT47H128M8HQ-3AT
AC Timing Operating Specifications
Table 11: AC Operating Specifications and Conditions
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = +1.5–1.9V, VDD = +1.5–1.9V
AC Characteristics
-25E
-25
-3E
-3
-37E
Units
Notes
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Clock
cycle time
CL = 6
tCK (avg)
2.5
8.0
2.5
8.0
–
ns
CL = 5
tCK (avg)
2.5
8.0
3.0
8.0
3.0
8.0
3.0
8.0
–
CL = 4
tCK (avg)
3.75
8.0
3.75
8.0
3.0
8.0
3.75
8.0
3.75
8.0
CL = 3
tCK (avg)
5.0
8.0
5.0
8.0
5.0
8.0
5.0
8.0
5.0
8.0
CK high-level width
tCH (avg)
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
tCK
CK low-level width
tCL (avg)
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
tCK
Half clock period
tHP
MIN = lesser of tCH and tCL
MAX = n/a
ps
Absolute tCK
tCK (abs)
MIN = tCK (AVG) MIN + tJITper (MIN)
MAX = tCK (AVG) MAX + tJITper (MAX)
ps
Absolute CK
high-level width
tCH (abs)
MIN = tCK (AVG) MIN × tCH (AVG) MIN + tJITdty (MIN)
MAX = tCK (AVG) MAX × tCH (AVG) MAX + tJITdty (MAX)
ps
Absolute CK
low-level width
tCL (abs)
MIN = tCK (AVG) MIN × tCL (AVG) MIN + tJITdty (MIN)
MAX = tCK (AVG) MAX × tCL (AVG) MAX + tJITdty (MAX)
ps
Clock
Jitter
Period jitter
tJITper
–100
100
–100
100
–125
125
–125
125
–125
125
ps
Half period
tJITdty
–100
100
–100
100
–125
125
–125
125
–125
125
ps
Cycle to cycle
tJITcc
200
250
ps
Cumulative error,
2 cycles
tERR2per
–150
150
–150
150
–175
175
–175
175
–175
175
ps
Cumulative error,
3 cycles
tERR3per
–175
175
–175
175
–225
225
–225
225
–225
225
ps
Cumulative error,
4 cycles
tERR4per
–200
200
–200
200
–250
250
–250
250
–250
250
ps
Cumulative error,
5 cycles
tERR5per
–200
200
–200
200
–250
250
–250
250
–250
250
ps
Cumulative error,
6–10 cycles
tERR6–10per
–300
300
–300
300
–350
350
–350
350
–350
350
ps
Cumulative error,
11–50 cycles
tERR11–50per
–450
450
–450
450
–450
450
–450
450
–450
450
ps
1Gb:
x4,
x8,
x16
1.55V
DDR2
SDRAM
AC
Timing
Operating
Specifications
PDF:
09005aef82b91d01
1GbDDR2_1_55V.PDF
Rev.
A
5/09
EN
29
Micron
Technology,
Inc.
reserves
the
right
to
change
products
or
specifications
without
notice.
2009
Micron
Technology,
Inc.
All
rights
reserved.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT47H128M8HQ-3EAT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
MT47H128M8HQ-3EIT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
MT47H128M8HQ-3EL 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
MT47H128M8HQ-3IT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
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