參數(shù)資料
型號: MT47H128M8HQ-3AT
元件分類: DRAM
英文描述: 128M X 8 DDR DRAM, 0.4 ns, PBGA60
封裝: 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60
文件頁數(shù): 44/129頁
文件大小: 9252K
代理商: MT47H128M8HQ-3AT
FBGA Package Capacitance
Table 4: Input Capacitance
Parameter
Symbol Min Max Units Notes
Input capacitance: CK, CK#
CCK
1.0
2.0
pF
Delta input capacitance: CK, CK#
CDCK
0.25
pF
Input capacitance: Address balls, bank address balls, CS#, RAS#, CAS#, WE#, CKE, ODT
CI
1.0
2.0
pF
Delta input capacitance: Address balls, bank address balls, CS#, RAS#, CAS#, WE#, CKE,
ODT
CDI
0.25
pF
Input/output capacitance: DQ, DQS, DM, NF
CIO
2.5
4.0
pF
Delta input/output capacitance: DQ, DQS, DM, NF
CDIO
0.5
pF
Notes: 1. This parameter is sampled. VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VREF = VSS, f = 100
MHz, TC = 25°C, VOUT(DC) = VDDQ/2, VOUT (peak-to-peak) = 0.1V. DM input is grouped
with I/O balls, reflecting the fact that they are matched in loading.
2. The capacitance per ball group will not differ by more than this maximum amount for
any given device.
3.
ΔC are not pass/fail parameters; they are targets.
4. Reduce MAX limit by 0.25pF for -25, -25E, and -187E speed devices.
5. Reduce MAX limit by 0.5pF for -3, -3E, -25, -25E, and -187E speed devices.
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
Packaging
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
21
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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