參數(shù)資料
型號： MT47H128M8HQ-3AT
元件分類： DRAM
英文描述： 128M X 8 DDR DRAM, 0.4 ns, PBGA60
封裝： 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60
文件頁數(shù)： 17/129頁
文件大小： 9252K
代理商： MT47H128M8HQ-3AT
Power-Down Mode
DDR2 SDRAM supports multiple power-down modes that allow significant power sav-
ings over normal operating modes. CKE is used to enter and exit different power-down
modes. Power-down entry and exit timings are shown in Figure 69 (page 114). Detailed
power-down entry conditions are shown in Figure 70 (page 116)–Figure 77 (page 119).
Table 43 (page 115) is the CKE Truth Table.
DDR2 SDRAM requires CKE to be registered HIGH (active) at all times that an access is
in progress—from the issuing of a READ or WRITE command until completion of the
burst. Thus, a clock suspend is not supported. For READs, a burst completion is defined
when the read postamble is satisfied; for WRITEs, a burst completion is defined when
the write postamble and tWR (WRITE-to-PRECHARGE command) or tWTR (WRITE-to-
READ command) are satisfied, as shown in Figure 72 (page 117) and Figure 73
(page 117) on Figure 73 (page 117). The number of clock cycles required to meet tWTR
is either two or tWTR/tCK, whichever is greater.
Power-down mode (see Figure 69 (page 114)) is entered when CKE is registered low
coincident with an NOP or DESELECT command. CKE is not allowed to go LOW during
a mode register or extended mode register command time, or while a READ or WRITE
operation is in progress. If power-down occurs when all banks are idle, this mode is
referred to as precharge power-down. If power-down occurs when there is a row active
in any bank, this mode is referred to as active power-down. Entering power-down deac-
tivates the input and output buffers, excluding CK, CK#, ODT, and CKE. For maximum
power savings, the DLL is frozen during precharge power-down. Exiting active power-
down requires the device to be at the same voltage and frequency as when it entered
power-down. Exiting precharge power-down requires the device to be at the same volt-
age as when it entered power-down; however, the clock frequency is allowed to change
The maximum duration for either active or precharge power-down is limited by the re-
fresh requirements of the device tRFC (MAX). The minimum duration for power-down
entry and exit is limited by the tCKE (MIN) parameter. The following must be main-
tained while in power-down mode: CKE LOW, a stable clock signal, and stable power
supply signals at the inputs of the DDR2 SDRAM. All other input signals are “Don’t
Care” except ODT. Detailed ODT timing diagrams for different power-down modes are
The power-down state is synchronously exited when CKE is registered HIGH (in con-
junction with a NOP or DESELECT command), as shown in Figure 69 (page 114).
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
Power-Down Mode
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
113
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT47H128M8HQ-3EAT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
MT47H128M8HQ-3EIT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
MT47H128M8HQ-3EL 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
MT47H128M8HQ-3IT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
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