參數(shù)資料
型號(hào)： MT46V64M4TG-75E
元件分類： DRAM
英文描述： 64M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝： 0.400 INCH, PLASTIC, TSOP-66
文件頁(yè)數(shù)： 74/83頁(yè)
文件大?。?/td> 2343K
代理商： MT46V64M4TG-75E
256Mb: x4, x8, x16
DDR SDRAM
09005aef8076894f
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MBDDRx4x8x16_2.fm - Rev. K 9/04 EN
76
2003 Micron Technology, Inc. All rights reserved.
Figure 48: Self Refresh Mode
NOTE:
1. Clock must be stable until after the SELF REFRESH command has been registered. A change in clock frequency is allowed
before Ta0, provided it is within the specified tCK limits. Regardless, the clock must be stable before exiting self refresh mode.
That is, the clock must be cycling within specifications by Ta0.
2. NOPs are interchangeable with DESELECT commands; AR = AUTO REFRESH command.
3. Auto refresh is not required at this point, but is highly recommended.
4. Device must be in the all banks idle state prior to entering self refresh mode.
5. tXSNR is required before any non-READ command can be applied; only NOP or DESELECT commands are allowed until Tb1.
6. tXSRD (200 cycles of a valid CK and CKE = high) is required before any READ command can be applied.
7. As a general rule, any time self refresh mode is exited, the DRAM may not re-enter the self refresh mode until all rows have
been refreshed via the AUTO REFRESH command at the distributed refresh rate, tREFI, or faster. However, self refresh mode
may be re-entered anytime after exiting, if the following conditions are all met:
a.
The DRAM had been in the Self Refresh Mode for a minimum of 200ms prior to exiting.
b.
tXSNR and tXSRD are not violated.
c.
At least two AUTO REFRESH commands are performed during each tREFI interval while the DRAM remains out of
Self Refresh mode.
8. If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit.
9. Once initialized, including during Self-Refresh mode, VREF must always be powered within the specified range.
CK1
CK#
COMMAND2
NOP
AR
ADDR
CKE
DQ
DM
DQS
NOP
tRP4
tCH
tCL
tCK
tIS
tIH
tIS
tIH
tIS
Enter Self Refresh Mode7
Exit Self Refresh Mode7
T0
T11
Ta1
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DON’T CARE
Ta01
tXSRD6
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NOP
VALID3
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tXSNR5
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Ta2
Tb1
Tb2
Tc1
VALID
tIS
tIH
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-5B
-6/6T
-75E/75Z
-75
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS
tCH
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55
tCK
tCL
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55
tCK
tCK (3)
5
7.5
nananana
na
ns
tCK (2.5)
6
13
6
13
7.5
13
7.5
13
ns
tCK (2)
7.5
13
7.5
13
7.5
13
10
13
ns
tIH
F
0.6
0.75
0.90
ns
tIS
F
0.6
0.75
0.90
ns
tIH
S
0.6
0.8
1
ns
tIS
S
0.6
0.8
1
ns
tRFC
707275
75
ns
tRP
15
20
ns
tVTD
000
0
ns
-5B
-6/6T
-75E/75Z
-75
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT46V64M4TG-75Z 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM
MT46V64M8 制造商:MICRON 制造商全稱:Micron Technology 功能描述:512Mb: x4, x8, x16 Double Data Rate SDRAM Features
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