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參數(shù)資料
| 型號： | MT46V64M4TG-75E |
| 元件分類： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP-66 |
| 文件頁數(shù)： | 61/83頁 |
| 文件大?。?/td> | 2343K |
| 代理商： | MT46V64M4TG-75E |
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256Mb: x4, x8, x16
DDR SDRAM
09005aef8076894f
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MBDDRx4x8x16_2.fm - Rev. K 9/04 EN
64
2003 Micron Technology, Inc. All rights reserved.
tDH for each 0.1 V/ns reduction in slew rate. For -
5B, -6 and -6T speed grades, slew rate must be
≥ 0.5 V/ns. If slew rate exceeds 4 V/ns, functional-
ity is uncertain.
32. VDD must not vary more than four percent if CKE
is not active while any bank is active.
33. The clock is allowed up to ±150ps of jitter. Each
timing parameter is allowed to vary by the same
amount.
34. tHP (MIN) is the lesser of tCL minimum and tCH
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
35. READs and WRITEs with auto precharge are not
allowed to be issued until tRAS (MIN) can be satis-
fied prior to the internal PRECHARGE command
being issued.
36. Any positive glitch must be less than 1/3 of the
clock cycle and not more than +400mV or 2.9V
(+300mV or 2.9V maximum for -5B), whichever is
less. Any negative glitch must be less than 1/3 of
the clock cycle and not exceed either -300mV or
2.2V, (2.4V for -5B) whichever is more positive.
The average cannot be below the +2.5V (2.6V for
-5B) minimum.
37. Normal output drive curves:
a. The full variation in driver pull-down current
from minimum to maximum process, temper-
ature, and voltage will lie within the outer
bounding lines of the V-I curve of Figure 36
b. The variation in driver pull-down current
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 36.
c. The full variation in driver pull-up current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 37.
d. The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of
Figure 37.
e. The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature. f ) The
full variation in the ratio of the nominal pull-
up to pull-down current should be unity ±10
percent, for device drain-to-source voltages
from 0.1V to 1.0V.
38. Reduced output drive curves:
a. The full variation in driver pull-down current
from minimum to maximum process, temper-
ature, and voltage will lie within the outer
bounding lines of the V-I curve of Figure 38.
b. The variation in driver pull-down current
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 38.
c. The full variation in driver pull-up current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 39.
d. The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of
Figure 39.
Figure 36: Full Drive Pull-Down
Characteristics
Figure 37: Full Drive Pull-Up
Characteristics
0
20
40
60
80
100
120
140
160
0.0
0.5
1.0
1.5
2.0
2.5
VOUT (V)
IOUT
(m
A
)
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
0.0
0.5
1.0
1.5
2.0
2.5
VDDQ - V OUT (V )
IOUT
(m
A
)
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PDF描述 |
|---|---|
| MT46V64M4FG-75Z | 64M X 4 DDR DRAM, 0.75 ns, PBGA60 |
| MT47H128M8HQ-3AT | 128M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| MT47H64M16HR-3IT | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| MT48H8M16LFB4-8IT:JTR | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| MT48LC4M32TG-10 | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V64M4TG-75Z | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M8 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:512Mb: x4, x8, x16 Double Data Rate SDRAM Features |
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