參數(shù)資料
型號： MT46V64M4TG-75E
元件分類： DRAM
英文描述： 64M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝： 0.400 INCH, PLASTIC, TSOP-66
文件頁數(shù)： 55/83頁
文件大小： 2343K
代理商： MT46V64M4TG-75E
256Mb: x4, x8, x16
DDR SDRAM
09005aef8076894f
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MBDDRx4x8x16_2.fm - Rev. K 9/04 EN
59
2003 Micron Technology, Inc. All rights reserved.
Table 26:
Electrical Characteristics and Recommended AC Operating Conditions
(-6/-6T/-75E)
Notes: 1–5, 14–17, 33; notes appear on pages 62–65; 0°C
≤ T
A ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
AC CHARACTERISTICS
-6 (FBGA)
-6T (TSOP)
-75E
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX UNITS NOTES
Access window of DQs from CK/CK#
tAC
-0.70
+0.70
-0.70
+0.70
-0.75
+0.75
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
30
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
30
Clock cycle time
CL = 2.5
tCK (2.5)
6
13
6
13
7.5
13
ns
45, 51
CL = 2
tCK (2)
7.5
13
7.5
13
7.5
13
ns
45, 51
DQ and DM input hold time relative to DQS
tDH
0.45
0.5
ns
26, 31
DQ and DM input setup time relative to DQS
tDS
0.45
0.5
ns
26, 31
DQ and DM input pulse width (for each input)
tDIPW
1.75
ns
31
Access window of DQS from CK/CK#
tDQSCK
-0.6
+0.6
-0.6
+0.6
-0.75
+0.75
ns
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS–DQ skew, DQS to last DQ valid, per group, per access
tDQSQ
0.4
0.45
0.5
ns
25, 26
WRITE command to first DQS latching transition
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK rising – setup time
tDSS
0.2
tCK
DQS falling edge from CK rising – hold time
tDSH
0.2
tCK
Half clock period
tHP
tCH,tCL
ns
34
Data-out high-impedance window from CK/CK#
tHZ
+0.7
+0.75
ns
18, 42
Data-out low-impedance window from CK/CK#
tLZ
-0.7
-0.75
ns
18, 42
Address and control input hold time (fast slew rate)
tIH
F
0.75
0.90
ns
Address and control input setup time (fast slew rate)
tIS
F
0.75
0.90
ns
Address and control input hold time (slow slew rate)
tIH
S
0.8
1
ns
14
Address and control input setup time (slow slew rate)
tIS
S
0.8
1
ns
14
Address and Control input pulse width (for each input)
tIPW
2.2
ns
LOAD MODE REGISTER command cycle time
tMRD
12
15
ns
DQ–DQS hold, DQS to first DQ to go non-valid, per access
tQH
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
ns
25, 26
Data hold skew factor
tQHS
0.5
0.55
0.75
ns
ACTIVE to PRECHARGE command
tRAS
42
70,000
42
70,000
40
120,000
ns
35, 53
ACTIVE to READ with auto precharge command
tRAP
15
ns
ACTIVE to ACTIVE/AUTO REFRESH command period
tRC
60
ns
AUTO REFRESH command period
tRFC
72
75
ns
49
ACTIVE to READ or WRITE delay
tRCD
15
ns
PRECHARGE command period
tRP
15
ns
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
43
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
43
ACTIVE bank a to ACTIVE bank b command
tRRD
12
15
ns
DQS write preamble
tWPRE
0.25
tCK
DQS write preamble setup time
tWPRES
0
ns
20, 21
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
19
Write recovery time
tWR
15
ns
Internal WRITE to READ command delay
tWTR
1
tCK
Data valid output window (DVW)
N/A
tQH - tDQSQ
ns
25
REFRESH to REFRESH command interval
tREFC
70.3
s
23
Average periodic refresh interval
tREFI
7.8
s
23
Terminating voltage delay to VDD
tVTD
0
ns
Exit SELF REFRESH to non-READ command
tXSNR
75
ns
Exit SELF REFRESH to READ command
tXSRD
200
tCK
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