參數(shù)資料
型號(hào)： MT46V64M4TG-75E
元件分類： DRAM
英文描述： 64M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝： 0.400 INCH, PLASTIC, TSOP-66
文件頁數(shù)： 48/83頁
文件大?。?/td> 2343K
代理商： MT46V64M4TG-75E
256Mb: x4, x8, x16
DDR SDRAM
09005aef8076894f
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MBDDRx4x8x16_2.fm - Rev. K 9/04 EN
52
2003 Micron Technology, Inc. All rights reserved.
Table 19:
IDD Specifications and Conditions (x4, x8; -6/-6T/-75E)
0°C
≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
Notes: 1–5, 10, 12, 14, 46; notes appear on pages 62–65; See also Table 24, IDD Test Cycle Times, on page 57
MAX
PARAMETER/CONDITION
SYMBOL
-6/6T
-75E
UNITS
NOTES
OPERATING CURRENT: One bank; active precharge;
tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing once per clock cycle; address and control inputs changing
once every two clock cycles
IDD0
125
mA
22, 47
OPERATING CURRENT: One bank; active-read precharge;
burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; address
and control inputs changing once per clock cycle
IDD1
170
160
mA
22, 47
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
power-down mode; tCK = tCK (MIN); CKE = (LOW)
IDD2P
4
mA
23, 32, 49
IDLE STANDBY CURRENT: CS# = HIGH; all banks are idle;
tCK = tCK (MIN); CKE = HIGH; address and other control inputs
changing once per clock
cycle; VIN = VREF for DQ, DQS, and DM
IDD2F
50
45
mA
50
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
power-down mode; tCK = tCK (MIN); CKE = LOW
IDD3P
30
25
mA
23, 32, 49
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
one bank active
; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and
DQS inputs changing twice per clock cycle; address and other
control inputs changing once per clock cycle
IDD3N
60
50
mA
22
OPERATING CURRENT: Burst = 2; READs; continuous burst;
one bank active; address and control inputs changing once per
clock cycle; tCK = tCK (MIN);
IOUT = 0mA
IDD4R
175
150
mA
22, 47
OPERATING CURRENT: Burst = 2; WRITEs; continuous burst;
one bank active; address and control inputs changing once per
clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing
twice per clock cycle
IDD4W
175
150
mA
22
AUTO REFRESH BURST CURRENT:
tREFC =tRC(MIN)
IDD5
255
235
mA
49
tREFC = 7.8s
IDD5A
6
mA
27, 49
SELF REFRESH CURRENT: CKE
≤ 0.2V
Standard
IDD6
44
mA
11
Low power (L)
IDD6A
22
mA
11
OPERATING CURRENT: Four-bank interleaving READs
(Burst = 4) with auto precharge, tRC = minimum tRC allowed;
tCK = tCK (MIN); address and control inputs change only during
active READ or WRITE commands
IDD7
410
350
mA
22, 48
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT46V64M4TG-75Z 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM
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