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參數(shù)資料
| 型號： | MT46V64M4TG-75E |
| 元件分類： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP-66 |
| 文件頁數(shù)： | 39/83頁 |
| 文件大?。?/td> | 2343K |
| 代理商： | MT46V64M4TG-75E |
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256Mb: x4, x8, x16
DDR SDRAM
09005aef8076894f
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MBDDRx4x8x16_2.fm - Rev. K 9/04 EN
44
2003 Micron Technology, Inc. All rights reserved.
NOTE:
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after
tXSNR has been met (if the pre-
vious state was self refresh).
2. This table describes alternate bank operation except where noted (i.e., the current state is for bank n and the com-
mands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given com-
mand is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no regis-
ter accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi-
nated.
Write:A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been ter-
minated
Read with Auto Precharge Enabled: See following text – 3a
Write with Auto Precharge Enabled: See following text – 3a
a. The read with auto precharge enabled or write with auto precharge enabled states can each be broken into two
parts: the access period and the precharge period. For read with auto precharge, the precharge period is defined as if
the same burst was executed with auto precharge disabled and then followed with the earliest possible PRECHARGE
command that still accesses all of the data in the burst. For write with auto precharge, the precharge period begins
when tWR ends, with tWR measured as if auto precharge was disabled. The access period starts with registration of
the command and ends where the precharge period (or tRP) begins.
Table 9:
Truth Table – Current State Bank n– Command to Bank m
Notes: 1–6; notes appear below and on next page
CURRENT STATE
CS#
RAS#
CAS#
WE#
COMMAND/ACTION
NOTES
Any
HX
X
DESELECT (NOP/continue previous operation)
LH
H
NO OPERATION (NOP/continue previous operation)
Idle
XX
X
Any Command Otherwise Allowed to Bank m
Row
Activating,
Active, or
Precharging
LL
H
ACTIVE (select and activate row)
LH
L
H
READ (select column and start READ burst)
7
LH
L
WRITE (select column and start WRITE burst)
7
LL
H
L
PRECHARGE
Read
(Auto-Precharge
Disabled)
LL
H
ACTIVE (select and activate row)
LH
L
H
READ (select column and start new READ burst)
7
LH
L
WRITE (select column and start WRITE burst)
7, 9
LL
H
L
PRECHARGE
Write
(Auto- Precharge
Disabled)
LL
H
ACTIVE (select and activate row)
LH
L
H
READ (select column and start READ burst)
7, 8
LH
L
WRITE (select column and start new WRITE burst)
7
LL
H
L
PRECHARGE
Read
(With Auto-
Precharge)
LL
H
ACTIVE (select and activate row)
LH
L
H
READ (select column and start new READ burst)
7, 3a
LH
L
WRITE (select column and start WRITE burst)
7, 9, 3a
LL
H
L
PRECHARGE
Write
(With Auto-
Precharge)
LL
H
ACTIVE (select and activate row)
LH
L
H
READ (select column and start READ burst)
7, 3a
LH
L
WRITE (select column and start new WRITE burst)
7, 3a
LL
H
L
PRECHARGE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT46V64M4FG-75Z | 64M X 4 DDR DRAM, 0.75 ns, PBGA60 |
| MT47H128M8HQ-3AT | 128M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| MT47H64M16HR-3IT | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| MT48H8M16LFB4-8IT:JTR | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| MT48LC4M32TG-10 | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V64M4TG-75Z | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M8 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:512Mb: x4, x8, x16 Double Data Rate SDRAM Features |
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