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256Mb: x4, x8, x16
DDR SDRAM
09005aef8076894f
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MBDDRx4x8x16_2.fm - Rev. K 9/04 EN
81
2003 Micron Technology, Inc. All rights reserved.
Figure 53: Write – DM Operation
NOTE:
1. DIn = data-in from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T8.
5. PRE = PRECHARGE; ACT = ACTIVE; RA = Row Address; and BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.
7. See Figure 43, Data Input Timing, on page 71, for detailed DQ timing.
8.
Although not required by the Micron device, JEDEC specifies that DQS be a valid HIGH, LOW or some point on a valid
transition on or before this clock edge (T3n).
CK
CK#
CKE
A10
BA0, BA1
tCK
tCH
tCL
tIS
tIH
tIS
tIH
tIS
tIH
RA
tRCD
tRAS
tRP
tWR
T0
T1
T2
T3
T4
T5
T5n
T6
T7
T8
T4n
NOP6
COMMAND5
3
ACT
RA
Col n
WRITE2
NOP6
ONE BANK
ALL BANKS
Bank x
PRE
Bank x
NOP6
tDQSL tDQSH tWPST
Bank x4
DQ1
DQS
DM
DI
b
tDS
tDH
DON’T CARE
TRANSITIONING DATA
tDQSS (NOM)
tWPRES tWPRE
x4: A0-A9, A11
x8: A0-A9
x16: A0-A8
x4: A12
x8: A11, A12
x16: A9, A11, A12
8
T3n
-5B
-6/6T
-75E/75Z
-75
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS
tCH
0.45 0.55 0.45 0.55 0.45
0.55
0.45
0.55
tCK
tCL
0.45 0.55 0.45 0.55 0.45
0.55
0.45
0.55
tCK
tCK (3)
5
7.5
na
ns
tCK (2.5)
6
13
6
13
7.5
13
7.5
13
ns
tCK (2)
7.5
13
7.5
13
7.5
13
10
13
ns
tDH
0,40
0.45
0.5
ns
tDS
0.40
0.45
0.5
ns
tDQSH 0.35
0.35
tCK
tDQSL
0.35
tCK
tDQSS
0.72 1.28 0.75 1.25 0.75
1.25
0.75
1.25
tCK
tDSS
0.2
tCK
tDSH
0.2
tCK
tIH
S
0.6
0.8
1
ns
tIS
S
0.6
0.8
1
ns
tRAS
40
70,000
42
70,000
40
120,000
40
120,000
ns
tRCD
15
20
ns
tRP
15
20
ns
tWPRE
.25
0.25
tCK
tWPRES
00
0
ns
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
tWR
15
ns
-5B
-6/6T
-75E/75Z
-75
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS