參數(shù)資料
型號(hào)： MT46V64M4FG-75Z
元件分類(lèi)： DRAM
英文描述： 64M X 4 DDR DRAM, 0.75 ns, PBGA60
封裝： 8 X 14 MM, PLASTIC, FBGA-60
文件頁(yè)數(shù)： 7/83頁(yè)
文件大?。?/td> 2343K
代理商： MT46V64M4FG-75Z
256Mb: x4, x8, x16
DDR SDRAM
09005aef8076894f
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MBDDRx4x8x16_2.fm - Rev. K 9/04 EN
15
2003 Micron Technology, Inc. All rights reserved.
the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operat-
ing mode.
All other combinations of values for A7–A12 are
reserved for future use and/or test modes. Test modes
and reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
Extended Mode Register
The extended mode register controls functions
beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 9. The extended mode register
is programmed via the LOAD MODE REGISTER com-
mand to the mode register (with BA0 = 1 and BA1 = 0)
and will retain the stored information until it is pro-
grammed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL. Anytime a
DLL reset occurs, 200 clock cycles with CKE high is
required before a READ command can be issued.
The extended mode register must be loaded when
all banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiat-
ing any subsequent operation. Violating either of these
requirements could result in unspecified operation.
Output Drive Strength
The normal drive strength for all outputs are speci-
fied to be SSTL_2, Class II. The x16 supports a pro-
grammable option for reduced drive. This option is
intended for the support of the lighter load and/or
point-to-point environments. The selection of the
reduced drive strength will alter the DQ pins and DQS
pins from SSTL_2, Class II drive strength to a reduced
drive strength, which is approximately 54 percent of
the SSTL_2, Class II drive strength.
DLL Enable/Disable
When the part is running without the DLL enabled,
device functionality may be altered. The DLL must be
enabled for normal operation. DLL enable is required
during power-up initialization and upon returning to
normal operation after having disabled the DLL for the
purpose of debug or evaluation. (When the device
exits self refresh mode, the DLL is enabled automati-
cally.) Any time the DLL is enabled, a DLL Reset and
200 clock cycles with CKE high must occur before a
READ command can be issued.
Figure 9: Extended Mode Register
Definition
NOTE:
1. E14 and E13 (BA1 and BA0) must be “0, 1” to select the
extended mode register vs. the base mode register.
2. The reduced drive strength option is not supported on
the x4 and x8 versions; it is only available on the x16
version.
3. The QFC# option is not supported.
Operating Mode
Reserved
0
–
0
–
Valid
–
0
1
DLL
Enable
Disable
DLL
11
01
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Extended Mode
Register (Ex)
Address Bus
9
7
65
4
3
8
2
1
0
E0
0
1
Drive Strength
Normal
Reduced
E12
E23
E0
E1,
Operating Mode
A10
A11
A12
BA1 BA0
10
11
12
13
14
E3
E4
0
–
0
–
0
–
0
–
0
–
E6 E5
E7
E8
E9
0
–
0
–
E10
E11
0
–
E12
DS
0
–
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