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參數(shù)資料
| 型號： | MT46V64M4FG-75Z |
| 元件分類： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, 0.75 ns, PBGA60 |
| 封裝： | 8 X 14 MM, PLASTIC, FBGA-60 |
| 文件頁數(shù)： | 36/83頁 |
| 文件大?。?/td> | 2343K |
| 代理商： | MT46V64M4FG-75Z |
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256Mb: x4, x8, x16
DDR SDRAM
09005aef8076894f
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MBDDRx4x8x16_2.fm - Rev. K 9/04 EN
41
2003 Micron Technology, Inc. All rights reserved.
Figure 32: Power-Down
NOTE:
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. CKE must not drop LOW during a column access. For a READ, this means CKE must stay HIGH until after the read post-
amble time; for a WRITE, CKE must stay HIGH until the WRITE recovery time (tWR) has been met.
6. Once initialized, including during self refresh mode, VREF must be powered within the specified range.
7. Upon exit of the self refresh mode, the DLL is automatically enabled, but a DLL reset must still occur. A minimum of 200
clock cycles is needed before applying a READ command for the DLL to lock. DESELECT or NOP commands should be
issued on any clock edges occurring during the tXSNR period.
tIS
No READ/WRITE
access in progress
Exit power-down mode
Enter power-down mode
CKE
CK
CK#
COMMAND
NOP
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
NOP
VALID
T0
T1
T2
Ta0
Ta1
Ta2
VALID
DON’T CARE
VALID
Table 7:
Truth Table – CKE
Notes: 1–6
CKEn-1
CKEn CURRENT STATE
COMMANDn
ACTIONn
NOTES
LL
Power-Down
X
Maintain Power-Down
Self Refresh
X
Maintain Self Refresh
L
H
Power-Down
DESELECT or NOP
Exit Power-Down
Self Refresh
DESELECT or NOP
Exit Self Refresh
7
H
L
All Banks Idle
DESELECT or NOP
Precharge Power-Down Entry
Bank(s) Active
DESELECT or NOP
Active Power-Down Entry
All Banks Idle
AUTO REFRESH
Self Refresh Entry
H
See Table 8 on page 42
相關(guān)PDF資料 |
PDF描述 |
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| MT47H128M8HQ-3AT | 128M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| MT47H64M16HR-3IT | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| MT48H8M16LFB4-8IT:JTR | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| MT48LC4M32TG-10 | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| MT48V8M16LFB4-8XT | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V64M4FJ-6 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M4FJ-6T | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M4FJ-75Z | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
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