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參數(shù)資料
| 型號： | MT46V64M4FG-75Z |
| 元件分類： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, 0.75 ns, PBGA60 |
| 封裝： | 8 X 14 MM, PLASTIC, FBGA-60 |
| 文件頁數(shù)： | 35/83頁 |
| 文件大?。?/td> | 2343K |
| 代理商： | MT46V64M4FG-75Z |
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256Mb: x4, x8, x16
DDR SDRAM
09005aef8076894f
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MBDDRx4x8x16_2.fm - Rev. K 9/04 EN
40
2003 Micron Technology, Inc. All rights reserved.
PRECHARGE
The PRECHARGE command, as shown in Figure 31,
is used to deactivate the open row in a particular bank
or the open row in all banks. The bank(s) will be avail-
able for a subsequent row access some specified time
(tRP) after the PRECHARGE command is issued. Input
A10 determines whether one or all banks are to be pre-
charged, and in the case where only one bank is to be
precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are
treated as “Don’t Care.” Once a bank has been pre-
charged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued
to that bank.
Figure 31: PRECHARGE Command
Power-Down (CKE Not Active)
Unlike SDR SDRAMs, DDR SDRAMs require CKE to
be active at all times that an access is in progress, from
the issuing of a READ or WRITE command until com-
pletion of the access. Thus, a clock suspend is not sup-
ported. For READs, an access completion is defined
when the read postamble is satisfied; for WRITEs, an
access completion is defined when the write recovery
time (tWR) is satisfied.
Power-down, shown in Figure 32, Power-Down, on
page 41, is entered when CKE is registered LOW and all
of the criteria listed in Table 7, on page 41, are met. If
power-down occurs when all banks are idle, this mode
is referred to as precharge power-down; if power-down
occurs when there is a row active in any bank, this
mode is referred to as active power-down. Entering
power-down deactivates the input and output buffers,
excluding CK, CK#, and CKE. For maximum power sav-
ings, the DLL is frozen during precharge power-down
mode. Exiting power-down requires the device to be at
the same voltage and frequency as when it entered
power-down. However, power-down duration is lim-
ited by the refresh requirements of the device (tREFC).
While in power-down, CKE LOW and a stable clock
signal must be maintained at the inputs of the DDR
SDRAM, while all other input signals are “Don’t Care.”
The power-down state is synchronously exited when
CKE is registered HIGH (in conjunction with a NOP or
DESELECT command). A valid executable command
may be applied one clock cycle later.
CS#
WE#
CAS#
RAS#
CKE
A10
BA0,1
HIGH
ALL BANKS
ONE BANK
BA
A0–A9, A11, A12
CK
CK#
BA = Bank Address (if A10 is LOW;
otherwise “Don’t Care”)
DON’T CARE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT47H128M8HQ-3AT | 128M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| MT47H64M16HR-3IT | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| MT48H8M16LFB4-8IT:JTR | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| MT48LC4M32TG-10 | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| MT48V8M16LFB4-8XT | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V64M4FJ-6 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M4FJ-6T | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M4FJ-75Z | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
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