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參數(shù)資料
| 型號： | MT46V64M4FG-75Z |
| 元件分類： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, 0.75 ns, PBGA60 |
| 封裝： | 8 X 14 MM, PLASTIC, FBGA-60 |
| 文件頁數(shù)： | 10/83頁 |
| 文件大?。?/td> | 2343K |
| 代理商： | MT46V64M4FG-75Z |
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256Mb: x4, x8, x16
DDR SDRAM
09005aef8076894f
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MBDDRx4x8x16_2.fm - Rev. K 9/04 EN
18
2003 Micron Technology, Inc. All rights reserved.
for each burst type in the Operation section of this
data sheet. The user must not issue another command
to the same bank until the precharge time (tRP) is
completed.
BURST TERMINATE
The BURST TERMINATE command is used to trun-
cate READ bursts (with auto precharge disabled). The
most recently registered READ command prior to the
BURST TERMINATE command will be truncated, as
shown in the Operation section of this data sheet. The
open page, which the READ burst was terminated
from, remains open.
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the DDR SDRAM and is analogous to CAS#-BEFORE-
RAS# (CBR) refresh in FPM/EDO DRAMs. This com-
mand is nonpersistent, so it must be issued each time
a refresh is required. All banks must be idle before an
AUTO REFRESH command is issued.
The addressing is generated by the internal refresh
controller. This makes the address bits a “Don’t Care”
during an AUTO REFRESH command. The 256Mb
DDR SDRAM requires AUTO REFRESH cycles at an
average interval of 7.8125s (maximum).
To allow for improved efficiency in scheduling and
switching between tasks, some flexibility in the abso-
lute refresh interval is provided. A maximum of eight
AUTO REFRESH commands can be posted to any
given DDR SDRAM, meaning that the maximum abso-
lute interval between any AUTO REFRESH command
and the next AUTO REFRESH command is 9 x 7.8125s
(70.3s). Note, the JEDEC specification only allows 8 x
7.8125s, thus the Micron specification exceeds the
JEDEC requirement by one clock. This maximum
absolute interval is to allow future support for DLL
updates internal to the DDR SDRAM to be restricted to
AUTO REFRESH cycles, without allowing excessive
drift in tAC between updates.
Although not a JEDEC requirement, to provide for
future functionality, CKE must be active (HIGH) dur-
ing the auto refresh period. The auto refresh period
begins when the AUTO REFRESH command is regis-
tered and ends tRFC later.
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the DDR SDRAM, even if the rest of the system
is powered down. When in the self refresh mode, the
DDR SDRAM retains data without external clocking.
The SELF REFRESH command is initiated like an
AUTO REFRESH command except CKE is disabled
(LOW). The DLL is automatically disabled upon enter-
ing SELF REFRESH and is automatically enabled upon
exiting SELF REFRESH. (A DLL reset and 200 clock
cycles must then occur before a READ command can
be issued.) Input signals except CKE are “Don’t Care”
during SELF REFRESH. VREF voltage is also required for
the full duration of the SELF REFRESH.
The procedure for exiting self refresh requires a
sequence of commands. First, CK and CK# must be
stable prior to CKE going back HIGH. Once CKE is
HIGH, the DDR SDRAM must have NOP commands
issued for tXSNR because time is required for the com-
pletion of any internal refresh in progress. A simple
algorithm for meeting both refresh and DLL require-
ments is to apply NOPs for tXSNR time, then a DLL
reset and NOPs for 200 additional clock cycles before
applying any other command.
相關(guān)PDF資料 |
PDF描述 |
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| MT47H128M8HQ-3AT | 128M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| MT47H64M16HR-3IT | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| MT48H8M16LFB4-8IT:JTR | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| MT48LC4M32TG-10 | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| MT48V8M16LFB4-8XT | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V64M4FJ-6 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M4FJ-6T | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M4FJ-75Z | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
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