參數(shù)資料
型號: MT46V128M4P-75ZLIT:C
元件分類: DRAM
英文描述: 128M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝: 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66
文件頁數(shù): 79/94頁
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
80
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Notes
Figure 41:
x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window
Notes: 1. DQ transitioning after DQS transition define tDQSQ window. LDQS defines the lower byte
and UDQS defines the upper byte.
2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with
DQS transition and ends with the last valid DQ transition.
4. tQH is derived from tHP: tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
6. The data valid window is derived for each DQS transition and is tQH minus tDQSQ.
7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
DQ (Last data valid)2
DQ2
LDQS1
DQ (Last data valid)2
DQ (First data no longer valid)2
DQ0 - DQ7 and LDQS, collectively6
T2
T2n
T3
T3n
CK
CK#
T1
T2
T3
T4
T2n
T3n
tQH4
tDQSQ3
Data Valid
window
Data Valid
window
DQ (Last data valid)7
DQ7
UDQS1
DQ (Last data valid)7
DQ (First data no longer valid)7
DQ8–DQ15 and UDQS, collectively6
T2
T2n
T3
T3n
tQH4
tDQSQ3
tHP5
tQH4
Data Valid
window
Data Valid
Window
Data Valid
Window
Data Valid
Window
Data Valid
Window
Upper
Byte
Lower
Byte
Data Valid
window
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