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參數(shù)資料
| 型號： | MT46V128M4P-75ZLIT:C |
| 元件分類： | DRAM |
| 英文描述： | 128M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66 |
| 文件頁數(shù)： | 71/94頁 |
| 文件大?。?/td> | 4179K |
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09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
73
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Notes
Figure 35:
Derating Data Valid Window (tQH - tDQSQ)
31. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If
the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be
added to tDS and tDH for each 100mv/ns reduction in slew rate. For -5B, -6 and -6T
speed grades, slew rate must be ≥ 0.5V/ns. If slew rate exceeds 4V/ns, functionality is
uncertain.
32. VDD must not vary more than 4 percent if CKE is not active while any bank is active.
33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by
the same amount.
34. tHP (MIN) is the lesser of tCL minimum and tCH minimum actually applied to the
device CK and CK# inputs, collectively, during bank active.
35. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN)
can be satisfied prior to the internal precharge command being issued.
36. Any positive glitch must be less than 1/3 of the clock cycle and not more than +400mV
or 2.9V (+300mV or 2.9V maximum for -5B), whichever is less. Any negative glitch
must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2V (2.4V for
-5B), whichever is more positive. The average cannot be below the +2.5V (2.6V for -5B)
minimum.
37. Normal output drive curves:
A. The full driver pull-down current variation from MIN to MAX process, tempera-
ture and voltage will lie within the outer bounding lines of the V-I curve of
B. The driver pull-down current variation, within nominal voltage and temperature
limits, is expected, but not guaranteed, to lie within the inner bounding lines of
the V-I curve of Figure 36 on page 74.
C. The full driver pull-up current variation from MIN to MAX process, temperature
and voltage will lie within the outer bounding lines of the V-I curve of Figure 37 on
3.0ns
2.5ns
2.0ns
1.5ns
1.0ns
50/50
49/51
48/53
46/54
47/53
45/55
-6T @ tCK = 7.5ns
-75E / -75 @ tCK = 7.5ns
-6 @ tCK = 6ns
-6T @ tCK = 6ns
-5B @ tCK = 5ns
1.48
1.45
1.43
1.40
1.38
1.35
2.75
2.60
2.56
2.53
2.45
2.41
2.38
2.68
2.35
2.31
2.28
2.13
2.20
2.16
2.43
2.10
2.07
2.04
1.89
1.86
1.83
1.80
1.98
1.95
2.00
1.97
1.94
1.91
1.88
1.73
1.70
1.82
1.79
1.58
1.55
Clock Duty Cycle
Data
V
alid
Window
2.71
2.46
1.53
2.64
2.39
1.92
1.76
1.85
1.60
1.50
2.49
2.50
2.24
2.01
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V128M4T67A3WC1 | 制造商:Micron Technology Inc 功能描述:128MX4 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays |
| MT46V128M4TG-5B/D | 制造商:Samsung Semiconductor 功能描述: |
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