參數(shù)資料
型號(hào)： MT46V128M4P-75ZLIT:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝： 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66
文件頁(yè)數(shù)： 61/94頁(yè)
文件大小： 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
64
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Electrical Specifications
Table 26:
Electrical Characteristics & Recommended AC Operating Conditions (-5B)
Notes: 1–5, 14–17, 33; notes appear on page 71–76; 0°C
≤ T
A ≤ +70°C; VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V
AC Characteristics
-5B
Units
Notes
Parameter
Symbol
Min
Max
Access window of DQ from CK/CK#
tAC
-0.70
+0.70
ns
CK high-level width
tCH
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
tCK
Clock cycle time
CL = 3
tCK (3)
5
7.5
ns
51
CL = 2.5
tCK (2.5)
6
13
ns
CL = 2
tCK (2)
7.5
13
ns
DQ and DM input hold time relative to DQS
tDH
0.40
ns
DQ and DM input setup time relative to DQS
tDS
0.40
ns
DQ and DM input pulse width (for each input)
tDIPW
1.75
ns
Access window of DQS from CK/CK#
tDQSCK
-0.60
+0.60
ns
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS–DQ skew, DQS to last DQ valid, per group, per access
tDQSQ
0.40
ns
WRITE command to first DQS latching transition
tDQSS
0.72
1.28
tCK
DQS falling edge to CK rising – setup time
tDSS
0.2
tCK
DQS falling edge from CK rising – hold time
tDSH
0.2
tCK
Half-clock period
tHP
tCH,tCL
ns
Data-out High-Z window from CK/CK#
tHZ
+0.70
ns
Data-out Low-Z window from CK/CK#
tLZ
-0.70
ns
Address and control input hold time (slew rate
≤ 0.5 V/ns)
tIH
F
0.60
ns
Address and control input setup time (slew rate
≤ 0.5 V/ns)
tIS
F
0.60
ns
Address and control input pulse width (for each input)
tIPW
2.2
ns
LOAD MODE REGISTER command cycle time
tMRD
10
ns
DQ–DQS hold, DQS to first DQ to go non-valid, per access
tQH
tHP
-tQHS
ns
Data hold skew factor
tQHS
0.50
ns
ACTIVE-to-PRECHARGE command
tRAS
40
70,000
ns
ACTIVE-to-READ with auto precharge command
tRAP
15
ns
ACTIVE-to-ACTIVE/AUTO REFRESH command period
tRC
55
ns
AUTO REFRESH command period
tRFC
70
ns
ACTIVE-to-READ or WRITE delay
tRCD
15
ns
PRECHARGE command period
tRP
15
ns
DQS read preamble
tRPRE
0.9
1.1
tCK
DQS read postamble
tRPST
0.4
0.6
tCK
ACTIVE bank a to ACTIVE bank b command
tRRD
10
ns
DQS write preamble
tWPRE
0.25
tCK
DQS write preamble setup time
tWPRES
0
ns
DQS write postamble
tWPST
0.4
0.6
tCK
Write recovery time
tWR
15
ns
Internal WRITE-to-READ command delay
tWTR
2
tCK
Data valid output window (DVW)
N/A
tQH - tDQSQ
ns
REFRESH-to-REFRESH command interval
tREFC
70.3
s
Average periodic refresh interval
tREFI
7.8
s
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT46V128M4T67A3WC1 制造商:Micron Technology Inc 功能描述:128MX4 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays
MT46V128M4TG-5B/D 制造商:Samsung Semiconductor 功能描述:
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