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Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
53
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Operations
This device supports concurrent auto precharge such that when a read with auto
precharge is enabled or a write with auto precharge is enabled any command to
other banks is allowed, as long as that command does not interrupt the read or write
data transfer already in process. In either case, all other related limitations apply
(e.g., contention between read data and write data must be avoided).
b. The minimum delay from a read or write command with auto precharge enabled, to
a command to a different bank is summarized below:.
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks
are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com-
mand.
Table 11:
Command Delays
CLRU = CAS latency (CL) rounded up to the next integer; BL = Burst length
From Command
To Command
Minimum Delay
(with Concurrent Auto Precharge)
WRITE w/AP
READ or READ w/AP
[1 + (BL/2)] × tCK + tWTR
WRITE or WRITE w/AP
(BL/2) × tCK
PRECHARGE
1 tCK
ACTIVE
1 tCK
READ w/AP
READ or READ w/AP
(BL/2) × tCK
WRITE or WRITE w/AP
[CLRU
+ (BL/2)] × tCK
PRECHARGE
1 tCK
ACTIVE
1 tCK