參數(shù)資料
型號(hào)： MT46V128M4P-75ZLIT:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝： 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66
文件頁數(shù)： 46/94頁
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
50
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Operations
Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 8 on page 49) and
after tXSNR has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank
and the commands shown are those allowed to be issued to that bank when in that state).
Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank.
COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should
be issued on any clock edge occurring during these states. Allowable commands to the
other bank are determined by its current state and Table 9 and according to Table 10 on
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is
met. Once tRP is met, the bank will be in the idle state.
Row activating: Starts with registration of an ACTIVE command and ends when tRCD is
met. Once tRCD is met, the bank will be in the “row active” state.
Read w/auto-precharge Enabled: Starts with registration of a READ command with auto
precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be
in the idle state.
Write w/auto-precharge Enabled: Starts with registration of a WRITE command with
auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank
will be in the idle state.
5. The following states must not be interrupted by any executable command; COMMAND
INHIBIT or NOP commands must be applied on each positive clock edge during these
states.
Table 9:
Truth Table – Current State Bank n - Command to Bank n
(Notes: 1-6; notes appear below and on next page)
Current
State
CS#
RAS# CAS#
WE#
Command/Action
Notes
Any
HX
X
DESELECT (NOP/continue previous operation)
LH
H
NO OPERATION (NOP/continue previous operation)
Idle
LL
H
ACTIVE (select and activate row)
LL
L
H
AUTO REFRESH
7
LL
L
LOAD MODE REGISTER
7
Row
active
LH
L
H
READ (select column and start READ burst)
10
LH
L
WRITE (select column and start WRITE burst)
10
LL
H
L
PRECHARGE (deactivate row in bank or banks)
8
Read
(Auto-
precharge
disabled)
LH
L
H
READ (select column and start new READ burst)
10
LH
L
WRITE (select column and start WRITE burst)
10, 12
LL
H
L
PRECHARGE (truncate READ burst, start PRECHARGE)
8
LH
H
L
BURST TERMINATE
9
Write
(Auto-
precharge
disabled)
LH
L
H
READ (select column and start READ burst)
10, 11
LH
L
WRITE (select column and start new WRITE burst)
10
LL
H
L
PRECHARGE (truncate WRITE burst, start PRECHARGE)
8, 11
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT46V128M4T67A3WC1 制造商:Micron Technology Inc 功能描述:128MX4 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays
MT46V128M4TG-5B/D 制造商:Samsung Semiconductor 功能描述:
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