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參數(shù)資料
| 型號： | MT46V128M4P-75ZLIT:C |
| 元件分類： | DRAM |
| 英文描述： | 128M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66 |
| 文件頁數(shù)： | 42/94頁 |
| 文件大小： | 4179K |
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09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
47
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Operations
PRECHARGE
The PRECHARGE command (Figure 31) is used to deactivate the open row in a particu-
lar bank or the open row in all banks. The bank(s) will be available for a subsequent row
access some specified time (tRP) after the PRECHARGE command is issued. Input A10
determines whether one or all banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be
precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been pre-
charged, it is in the idle state and must be activated prior to any READ or WRITE com-
mands being issued to that bank.
Figure 31:
PRECHARGE Command
Note:
BA = Bank Address (if A10 is LOW; otherwise “Don’t Care”).
Power-Down (CKE Not Active)
Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in
progress, from the issuing of a READ or WRITE command until completion of the access.
Thus a clock suspend is not supported. For READs, an access completion is defined
when the read postamble is satisfied; for WRITEs, an access completion is defined when
the write recovery time (tWR) is satisfied.
Power-down, as shown in Figure 32 on page 48, is entered when CKE is registered LOW
and all Table 8 (page 49) criteria are met. If power-down occurs when all banks are idle,
this mode is referred to as precharge power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as active power-down. Entering power-
down deactivates the input and output buffers, excluding CK, CK#, and CKE. For maxi-
mum power savings, the DLL is frozen during precharge power-down mode. Exiting
CS#
WE#
CAS#
RAS#
CKE
A10
BA0,1
HIGH
ALL BANKS
ONE BANK
BA
A0–A9, A11, A12
CK
CK#
DON’T CARE
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PDF描述 |
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| MT46V64M4TG-75E | 64M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| MT46V64M4FG-75Z | 64M X 4 DDR DRAM, 0.75 ns, PBGA60 |
| MT47H128M8HQ-3AT | 128M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| MT47H64M16HR-3IT | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| MT48H8M16LFB4-8IT:JTR | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V128M4T67A3WC1 | 制造商:Micron Technology Inc 功能描述:128MX4 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays |
| MT46V128M4TG-5B/D | 制造商:Samsung Semiconductor 功能描述: |
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