- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄296642 > MT46V128M4P-75ZLIT:C 128M X 4 DDR DRAM, 0.75 ns, PDSO66 PDF資料下載
參數(shù)資料
| 型號： | MT46V128M4P-75ZLIT:C |
| 元件分類： | DRAM |
| 英文描述： | 128M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66 |
| 文件頁數(shù)： | 19/94頁 |
| 文件大?。?/td> | 4179K |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
26
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 11:
Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK
≤3
READs
READ bursts are initiated with a READ command, as shown in Figure 12 on page 27.
The starting column and bank addresses are provided with the READ command and
auto precharge is either enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst.
Note:
For the READ commands used in the following illustrations, auto precharge is dis-
abled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CAS latency after the READ command. Each subsequent data-
out element will be valid nominally at the next positive or negative clock edge (i.e., at the
next crossing of CK and CK#). Figure 13 on page 28 shows general timing for each possi-
ble CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The
initial LOW state on DQS is known as the read preamble; the LOW state coincident with
the last data-out element is known as the read postamble.
Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out
window hold), the valid data window are depicted in Figure 40 on page 79 and Figure 41
(data-out transition skew to CK) is depicted in Figure 42 on page 81.
Data from any READ burst may be concatenated with or truncated with data from a sub-
sequent READ command. In either case, a continuous flow of data can be maintained.
The first data element from the new burst follows either the last element of a completed
burst or the last desired data element of a longer burst which is being truncated. The
new READ command should be issued x cycles after the first READ command, where x
equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 14 on page 29. A READ command can be initiated
on any clock cycle following a previous READ command. Nonconsecutive read data is
shown for illustration in Figure 15 on page 30. Full-speed random read accesses within a
page (or pages) can be performed, as shown in Figure 16 on page 31.
t
COMMAND
BA0, BA1
ACTACT
NOP
RRD
tRCD
CK
CK#
Bank x
Bank y
A0-A12
Row
NOP
RD/WR
NOP
Bank y
Col
NOP
T0
T1
T2
T3
T4
T5
T6
T7
DON’T CARE
NOP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT46V64M4TG-75E | 64M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| MT46V64M4FG-75Z | 64M X 4 DDR DRAM, 0.75 ns, PBGA60 |
| MT47H128M8HQ-3AT | 128M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| MT47H64M16HR-3IT | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| MT48H8M16LFB4-8IT:JTR | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V128M4T67A3WC1 | 制造商:Micron Technology Inc 功能描述:128MX4 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays |
| MT46V128M4TG-5B/D | 制造商:Samsung Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。