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| 型號(hào)： | MT46V128M4P-75L:C |
| 元件分類： | DRAM |
| 英文描述： | 128M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66 |
| 文件頁數(shù)： | 85/94頁 |
| 文件大?。?/td> | 4179K |
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09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
86
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Timing Diagrams
Figure 47:
Auto Refresh Mode
Notes: 1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank
Address.
2. NOP commands are shown for ease of illustration; other valid commands may be possible
at these times. CKE must be active during clock positive transitions.
3. NOP or COMMAND INHIBIT are the only commands allowed until after tRFC time, CKE
must be active during clock positive transitions.
4. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is
active (i.e., must precharge all active banks).
5. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
6. The second AUTO REFRESH is not required and is only shown as an example of two back-
to-back AUTO REFRESH commands.
CK
CK#
COMMAND1
NOP2
VALID
NOP 2
NOP2
PRE
CKE
RA
A0-A9,
A11, A121
A101
BA0, BA11
Bank(s)4
BA
AR
NOP2, 3
AR6
NOP2, 3
ACT
NOP2
ONE BANK
ALL BANKS
CK
tCH
tCL
tIS
tIH
tIS
tIH
RA
DQ5
DM5
DQS5
tRFC5
tRP
tRFC
T0
T1
T2
T3
T4
Ta0
Tb0
Ta1
Tb1Tb2
DON’T CARE
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| MT46V128M4P-75ZLIT:C | 128M X 4 DDR DRAM, 0.75 ns, PDSO66 |
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT46V128M4T67A3WC1 | 制造商:Micron Technology Inc 功能描述:128MX4 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays |
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