參數(shù)資料
型號： MT46V128M4P-75L:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝： 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66
文件頁數(shù)： 83/94頁
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
84
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Timing Diagrams
Figure 45:
Initialize and Load Mode Registers
Notes: 1. VTT is not applied directly to the device; however, tVTD should be greater than or equal to zero
to avoid device latch-up. VDDQ, VTT, and VREF, must be equal to or less than VDD + 0.3V. Alterna-
tively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0V, provided a mini-
mum of 42 ohms of series resistance is used between the VTT supply and the input pin. Once
initialized, VREF must always be powered with in specified range.
2. Reset the DLL with A8 = H while programming the operating parameters.
3. tMRD is required before any command can be applied (during MRD time only NOPs or
deselects are allowed), and 200 cycles of CK are required before a READ command can be
issued.
4. The two AUTO REFRESH commands at Td0 and Te0 may be applied following the LOAD
MODE REGISTER (LMR) command at Ta0.
5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8
= L) prior to activating any bank. If another LMR command is issued, the same operating param-
eters, previously issued, must be used.
6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO
REFRESH command, ACT = ACTIVE command, RA = Row Address, BA = Bank Address.
tVTD1
CKE
LVCMOS
LOW LEVEL
DQ
BA0, BA1
200 cycles of CK3
Load Extended
Mode Register
Load Mode
Register2
tMRD
tRP
tRFC
tRFC5
tIS
Power-up: VDD and CK stable
T = 200s
High-Z
tIH
DM
DQS
High-Z
A0–A9,
A11, A12
RA
A10
ALL BANKS
CK
CK#
tCH
tCL
tCK
VTT1
VREF
VDD
VDDQ
COMMAND6
LMR
NOP
PRE
LMR
AR
ACT5
tIS tIH
BA0 = H,
BA1 = L
tIS
tIH
tIS tIH
BA0 = L,
BA1 = L
tIS
tIH
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CODE
tIS
tIH
CODE
CODE 4
PRE
ALL BANKS
tIS
tIH
T0
T1
Ta0
Tb0
Tc0
Td0
Te0
Tf0
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DON’T CARE
BA
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RA
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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