參數(shù)資料
型號(hào)： MT46V128M4P-75L:C
元件分類(lèi)： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝： 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66
文件頁(yè)數(shù)： 70/94頁(yè)
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
72
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Notes
16. Inputs are not recognized as valid until VREF stabilizes. Once initialized, including self
refresh mode, VREF must be powered within specified range. Exception: during the
period before VREF stabilizes, CKE < 0.3 × VDDQ is recognized as LOW.
17. The output timing reference level, as measured at the timing reference point (indi-
cated in Note 3) is VTT.
18. tHZ and tLZ transitions occur in the same access time windows as data valid transi-
tions. These parameters are not referenced to a specific voltage level, but specify
when the device output is no longer driving (HZ) or begins driving (LZ).
19. The intent of the “Don’t Care” state after completion of the postamble is the DQS-
driven signal should either be HIGH, LOW, or High-Z, and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions HIGH (above VIHDC (MIN) then it must not transition LOW (below
VIH(DC) prior to tDQSH (MIN).
20. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE com-
mand. The case shown (DQS going from High-Z to logic LOW) applies when no
WRITEs were previously in progress on the bus. If a previous WRITE was in progress,
DQS could be HIGH during this time, depending on tDQSS.
22. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the
minimum absolute value for the respective parameter. tRAS (MAX) for IDD measure-
ments is the largest multiple of tCK that meets the maximum absolute value for tRAS.
23. The refresh period is 64ms. This equates to an average refresh rate of 7.8125s. How-
ever, an AUTO REFRESH command must be asserted at least once every 70.3s; burst
refreshing or posting by the DRAM controller greater than 8 REFRESH cycles is not
allowed.
24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this
maximum amount for any given device.
25. The data valid window is derived by achieving other specifications - tHP (tCK/2),
tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct propor-
tion to the clock duty cycle and a practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of 45/55, because functionality is
uncertain when operating beyond a 45/55 ratio. The data valid window derating
curves are provided in Figure 35 on page 73 for duty cycles ranging between 50/50
and 45/55.
26. Referenced to each output group: x4 = DQS with DQ0–DQ3; x8 = DQS with DQ0–DQ7;
x16 = LDQS with DQ0–DQ7; and UDQS with DQ8–DQ15.
27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH
during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during
standby).
28. To maintain a valid level, the transitioning edge of the input must:
A. Sustain a constant slew rate from the current AC level through to the target AC
level, VIL(AC) or VIH(AC).
B. Reach at least the target AC level.
C. After the AC target level is reached, continue to maintain at least the target DC
level, VIL(DC) or VIH(DC).
29. The Input capacitance per pin group will not differ by more than this maximum
amount for any given device.
30. CK and CK# input slew rate must be ≥ 1V/ns (≥ 2V/ns if measured differentially).
相關(guān)PDF資料
PDF描述
MT46V128M4P-75ZLIT:C 128M X 4 DDR DRAM, 0.75 ns, PDSO66
MT46V64M4TG-75E 64M X 4 DDR DRAM, 0.75 ns, PDSO66
MT46V64M4FG-75Z 64M X 4 DDR DRAM, 0.75 ns, PBGA60
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT46V128M4T67A3WC1 制造商:Micron Technology Inc 功能描述:128MX4 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays
MT46V128M4TG-5B/D 制造商:Samsung Semiconductor 功能描述:
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