參數(shù)資料
型號： MT46V128M4P-75L:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝： 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66
文件頁數(shù)： 48/94頁
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
52
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Operations
Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after
tXSNR has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted (i.e., the current state is
for bank n and the commands shown are those allowed to be issued to bank m, assuming
that bank m is in such a state that the given command is allowable). Exceptions are cov-
ered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated
Read with auto precharge enabled: See following text – 3a
Write with auto precharge enabled: See following text – 3a
a. The read with auto precharge enabled or write with auto precharge enabled states
can each be broken into two parts: the access period and the precharge period. For
read with auto precharge, the precharge period is defined as if the same burst was
executed with auto precharge disabled and then followed with the earliest possible
PRECHARGE command that still accesses all of the data in the burst. For write with
auto precharge, the precharge period begins when tWR ends, with tWR measured as
if auto precharge was disabled. The access period starts with registration of the com-
mand and ends where the precharge period (or tRP) begins.
Table 10:
Truth Table – Current State Bank n - Command to Bank m
Notes: 1-6; notes appear below and on next page
Current State
CS#
RAS#
CAS#
WE#
Command/Action
Notes
Any
HX
X
DESELECT (NOP/continue previous operation)
LH
H
NO OPERATION (NOP/continue previous operation)
Idle
XX
X
Any Command Otherwise Allowed to Bank m
Row
activating,
active, or
precharging
LL
H
ACTIVE (select and activate row)
LH
L
H
READ (select column and start READ burst)
7
LH
L
WRITE (select column and start WRITE burst)
7
LL
H
L
PRECHARGE
Read
(Auto-
Precharge
Disabled)
LL
H
ACTIVE (select and activate row)
LH
L
H
READ (select column and start new READ burst)
7
LH
L
WRITE (select column and start WRITE burst)
7, 9
LL
H
L
PRECHARGE
Write
(auto-
precharge
disabled)
LL
H
ACTIVE (select and activate row)
LH
L
H
READ (select column and start READ burst)
7, 8
LH
L
WRITE (select column and start new WRITE burst)
7
LL
H
L
PRECHARGE
Read
(with auto-
precharge)
LL
H
ACTIVE (select and activate row)
LH
L
H
READ (select column and start new READ burst)
7, 3
LH
L
WRITE (select column and start WRITE burst)
7, 9, 3
LL
H
L
PRECHARGE
Write
(with auto-
precharge)
LL
H
ACTIVE (select and activate row)
LH
L
H
READ (select column and start READ burst)
7, 3
LH
L
WRITE (select column and start new WRITE burst)
7, 3
LL
H
L
PRECHARGE
相關(guān)PDF資料
PDF描述
MT46V128M4P-75ZLIT:C 128M X 4 DDR DRAM, 0.75 ns, PDSO66
MT46V64M4TG-75E 64M X 4 DDR DRAM, 0.75 ns, PDSO66
MT46V64M4FG-75Z 64M X 4 DDR DRAM, 0.75 ns, PBGA60
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT46V128M4T67A3WC1 制造商:Micron Technology Inc 功能描述:128MX4 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays
MT46V128M4TG-5B/D 制造商:Samsung Semiconductor 功能描述:
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