- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄296642 > MT46V128M4P-75L:C 128M X 4 DDR DRAM, 0.75 ns, PDSO66 PDF資料下載
參數(shù)資料
| 型號： | MT46V128M4P-75L:C |
| 元件分類： | DRAM |
| 英文描述： | 128M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66 |
| 文件頁數(shù)： | 44/94頁 |
| 文件大?。?/td> | 4179K |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁當(dāng)前第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
49
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Operations
Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous
clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COM-
MANDn.
4. All states and sequences not shown are illegal or reserved.
5. CKE must not drop LOW during a column access. For a READ, this means CKE must stay
HIGH until after the read postamble time; for a WRITE, CKE must stay HIGH until the
WRITE recovery time (tWR) has been met.
6. Once initialized, including during self refresh mode, VREF must be powered within the
specified range.
7. Upon exit of the self refresh mode the DLL is automatically enabled. A minimum of 200
clock cycles is needed before applying a READ command for the DLL to lock. DESELECT or
NOP commands should be issued on any clock edges occurring during the tXSNR period.
Table 8:
Truth Table – CKE
Notes: 1–6
CKEn-1
CKEn
Current State
Commandn
Actionn
Notes
L
Power-Down
X
Maintain power-down
Self refresh
X
Maintain self refresh
L
H
Power-Down
DESELECT or NOP
Exit power-down
Self refresh
DESELECT or NOP
Exit self refresh
7
H
L
All banks idle
DESELECT or NOP
Precharge power-down entry
Bank(s) active
DESELECT or NOP
Active power-down entry
All banks idle
AUTO REFRESH
Self refresh entry
H
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT46V128M4P-75ZLIT:C | 128M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| MT46V64M4TG-75E | 64M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| MT46V64M4FG-75Z | 64M X 4 DDR DRAM, 0.75 ns, PBGA60 |
| MT47H128M8HQ-3AT | 128M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| MT47H64M16HR-3IT | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V128M4T67A3WC1 | 制造商:Micron Technology Inc 功能描述:128MX4 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays |
| MT46V128M4TG-5B/D | 制造商:Samsung Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。