參數(shù)資料
型號(hào): MT46V128M4P-75L:C
元件分類(lèi): DRAM
英文描述: 128M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝: 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66
文件頁(yè)數(shù): 35/94頁(yè)
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
40
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 24:
Random WRITE Cycles
Notes: 1. DI b, etc. = data-in for column b, etc.
2. Symbol b', etc. = the next data-in following DI b, etc., according to the programmed burst
order.
3. Programmed BL = 2, 4, or 8 in cases shown.
4. Each WRITE command may be to any bank.
tDQSS (NOM)
CK
CK#
COMMAND
WRITE
NOP
ADDRESS
Bank,
Col b
Bank,
Col x
Bank,
Col n
Bank,
Col g
WRITE
Bank,
Col a
T0
T1
T2
T3
T2n
T4
T5
T4n
T1n
T3n
T5n
DQ
DQS
DM
DI
b
DI
b'
DI
x
DI
x'
DI
n
DI
n'
DI
a
DI
a'
DI
g
DI
g'
DON’T CARE
TRANSITIONING DATA
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