參數(shù)資料
型號： MT46V128M4P-75L:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝： 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66
文件頁數(shù)： 27/94頁
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
33
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 18:
READ-to-WRITE
Notes: 1. DO n = data-out from column n.
2. DI b = data-in from column b.
3. BL = 4 in the cases shown (applies for bursts of 8 as well; if BL = 2, the BST command shown
can be NOP).
4. One subsequent element of data-out appears in the programmed order following DO n.
5. Data-in elements are applied following DI b in the programmed order.
6. Shown with nominal tAC, tDQSCK, and tDQSQ.
7. BST = BURST TERMINATE command, page remains open.
CK
CK#
COMMAND
READ
BST7
NOP
ADDRESS
Bank,
Col n
WRITE
Bank,
Col b
T0
T1
T2
T3
T2n
T4
T5
T4n
T5n
DQ
DQS
DM
t
(NOM)
DQSS
DI
b
CK
CK#
COMMAND
READ
BST7
NOP
WRITE
NOP
ADDRESS
Bank a,
Col n
NOP
T0
T1
T2
T3
T3n
T4
T5
T5n
DQ
DQS
DO
n
DM
DON’T CARE
TRANSITIONING DATA
DO
n
t
(NOM)
DQSS
CK
CK#
COMMAND
READ
BST7
NOP
ADDRESS
Bank,
Col n
WRITE
Bank,
Col b
T0
T1
T2
T3
T2n
T4
T5
T5n
DQ
DQS
DM
t
(NOM)
DQSS
DI
b
DO
n
NOP
CL = 2.5
CL = 2
T3n
CL = 3
DI
b
相關(guān)PDF資料
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MT46V128M4P-75ZLIT:C 128M X 4 DDR DRAM, 0.75 ns, PDSO66
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT46V128M4T67A3WC1 制造商:Micron Technology Inc 功能描述:128MX4 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays
MT46V128M4TG-5B/D 制造商:Samsung Semiconductor 功能描述:
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