參數(shù)資料
型號： MT46V128M4FN-75E:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PBGA60
封裝： 10 X 12.50 MM, FBGA-60
文件頁數(shù)： 86/94頁
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
87
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Timing Diagrams
Figure 48:
Self Refresh Mode
Notes: 1. Clock must be stable until after the SELF REFRESH command has been registered. A change
in clock frequency is allowed before Ta0, provided it is within the specified tCK limits.
Regardless, the clock must be stable before exiting self refresh mode. That is, the clock
must be cycling within specifications by Ta0.
2. NOPs are interchangeable with DESELECT commands, AR = AUTO REFRESH command.
3. Auto refresh is not required at this point, but is highly recommended.
4. Device must be in the all banks idle state prior to entering self refresh mode.
5. tXSNR is required before any non-READ command can be applied. That is only NOP or
DESELECT commands are allowed until Tb1.
6. tXSRD (200 cycles of a valid clock with CKE = HIGH) is required before any READ command
can be applied.
7. As a general rule, any time self refresh mode is exited, the DRAM may not re-enter the self
refresh mode until all rows have been refreshed via the AUTO REFRESH command at the
distributed refresh rate, tREFI, or faster. However, the following exception is allowed. Self
refresh mode may be re-entered anytime after exiting, if the following conditions are all
met:
A.
The DRAM had been in the self refresh mode for a minimum of 200ms prior to exit-
ing.
B.
tXSNR and tXSRD are not violated.
C.
At least two AUTO REFRESH commands are performed during each tREFI interval
while the DRAM remains out of Self Refresh mode.
8. If the clock frequency is changed during self refresh mode, a DLL reset is required upon
exit.
9. Once the device is initialized, VREF must always be powered within specified range.
CK1
CK#
COMMAND2
NOP
AR
ADDR
CKE
DQ
DM
DQS
NOP
tRP4
tCH
tCL
tCK
tIS
tIH
tIS
tIH
tIS
Enter Self Refresh Mode7
Exit Self Refresh Mode7
T0
T11
Ta1
DON’T CARE
Ta01
tXSRD6
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VALID3
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Ta2
Tb1Tb2Tc1
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tIS
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VALID
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