參數(shù)資料
型號： MT46V128M4FN-75E:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PBGA60
封裝： 10 X 12.50 MM, FBGA-60
文件頁數(shù)： 63/94頁
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
66
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Electrical Specifications
Table 27:
Electrical Characteristics and Recommended AC Operating Conditions (-6/-6T/-75E)
Notes: 1–5, 14–17, 33; notes appear on page 71–76; 0°C
≤ T
A ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
AC Characteristics
-6 (FBGA)
-6T (TSOP)
-75E
Units Notes
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Access window of DQ from CK/CK#
tAC
-0.70
+0.70
-0.70
+0.70
-0.75
+0.75
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock cycle time
CL = 2.5
tCK (2.5)
6
13
6
13
7.5
13
ns
CL = 2
tCK (2)
7.5
13
7.5
13
7.5
13
ns
DQ and DM input hold time relative to DQS
tDH
0.45
0.5
ns
DQ and DM input setup time relative to DQS
tDS
0.45
0.5
ns
DQ and DM input pulse width (for each input)
tDIPW
1.75
ns
Access window of DQS from CK/CK#
tDQSCK
-0.6
+0.6
-0.6
+0.6
-0.75
+0.75
ns
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS-DQ skew, DQS to last DQ valid, per group, per
access
tDQSQ
0.4
0.45
0.5
ns
WRITE command-to-first DQS latching transition
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK rising - setup time
tDSS
0.2
tCK
DQS falling edge from CK rising - hold time
tDSH
0.2
tCK
Half-clock period
tHP
tCH,
tCL
tCH,
tCL
tCH,
tCL
ns
Data-out High-Z window from CK/CK#
tHZ
+0.7
+0.75
ns
Data-out Low-Z window from CK/CK#
tLZ
-0.7
-0.75
ns
Address and control input hold time (fast slew rate)
tIH
F
.75
.90
ns
Address and control input setup time (fast slew rate)
tIS
F
.75
.90
ns
Address and control input hold time (slow slew rate)
tIH
S
0.8
1
ns
Address and control input setup time (slow slew
rate)
tIS
S
0.8
1
ns
Address and Control input pulse width (for each
input)
tIPW
2.2
ns
LOAD MODE REGISTER command cycle time
tMRD
12
15
ns
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
tQH
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
ns
Data Hold Skew Factor
tQHS
0.50
0.55
0.75
ns
ACTIVE-to-PRECHARGE command
tRAS
42
70,00
0
42
70,00
0
40
120,00
0
ns
ACTIVE-to-READ with auto precharge command
tRAP
15
ns
ACTIVE-to-ACTIVE/AUTO REFRESH command period
tRC
60
ns
AUTO REFRESH command period
tRFC
72
75
ns
ACTIVE-to-READ or WRITE delay
tRCD
15
ns
PRECHARGE command period
tRP
15
ns
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
ACTIVE bank a to ACTIVE bank b command
tRRD
12
15
ns
DQS write preamble
tWPRE
0.25
tCK
DQS write preamble setup time
tWPRES
0
ns
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
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