參數(shù)資料
型號(hào)： MT46V128M4FN-75E:C
元件分類(lèi)： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PBGA60
封裝： 10 X 12.50 MM, FBGA-60
文件頁(yè)數(shù)： 43/94頁(yè)
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
48
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Operations
power-down requires the device to be at the same voltage and frequency as when it
entered power-down. However, power-down duration is limited by the refresh require-
ments of the device (tREFC).
While in power-down, CKE LOW and a stable clock signal must be maintained at the
inputs of the DDR SDRAM, while all other input signals are “Don’t Care.” The power-
down state is synchronously exited when CKE is registered HIGH (in conjunction with a
NOP or DESELECT command). A valid executable command may be applied one clock
cycle later.
Figure 32:
Power-Down
tIS
No READ/WRITE
access in progress
Exit power-down mode
Enter power-down mode
CKE
CK
CK#
COMMAND
NOP
(
)
(
)
(
)
(
)
(
)
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)
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)
(
)
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)
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)
NOP
VALID
T0
T1
T2
Ta0
Ta1
Ta2
VALID
DON’T CARE
VALID
Ta3
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