參數(shù)資料
型號： MT46V128M4FN-75E:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PBGA60
封裝： 10 X 12.50 MM, FBGA-60
文件頁數(shù)： 41/94頁
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
46
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 30:
WRITE-to-Precharge – Odd Number of Data, Interrupting
Notes: 1. DI b = data-in for column b.
2. An interrupted burst of 8 is shown; one data element is written.
3. tWR is referenced from the first positive CK edge after the last data-in pair.
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T4 and T4n (nominal case) to register DM.
6. If the burst of 4 was used, DQS and DM would not be required at T3, T3n, T4 and T4n.
7. PRE = PRECHARGE command.
tDQSS
tDQSS (NOM)
CK
CK#
COMMAND
WRITE
NOP
PRE7
NOP
ADDRESS
Bank a,
Col b
Bank,
(a or all)
NOP
T0
T1
T2
T3
T2n
T4
T5
T1n
T6
tWR
tRP
DQ
DQS
DM
DI
b
tDQSS
tDQSS (MIN)
DQ
DQS
DM
tDQSS
tDQSS (MAX)
DQ
DQS
DM
DI
b
DI
b
DON’T CARE
TRANSITIONING DATA
T3n
T4n
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